H8/3064 Просмотр технического описания (PDF) - Renesas Electronics
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H8/3064 Datasheet PDF : 1021 Pages
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14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 469
14.2.2 A/D Control/Status Register (ADCSR) ............................................................... 470
14.2.3 A/D Control Register (ADCR) ............................................................................ 472
14.3 CPU Interface ................................................................................................................... 473
14.4 Operation .......................................................................................................................... 475
14.4.1 Single Mode (SCAN = 0) .................................................................................... 475
14.4.2 Scan Mode (SCAN = 1)....................................................................................... 477
14.4.3 Input Sampling and A/D Conversion Time ......................................................... 479
14.4.4 External Trigger Input Timing............................................................................. 480
14.5 Interrupts........................................................................................................................... 481
14.6 Usage Notes ...................................................................................................................... 481
Section 15 D/A Converter................................................................................................. 487
15.1 Overview........................................................................................................................... 487
15.1.1 Features................................................................................................................ 487
15.1.2 Block Diagram..................................................................................................... 488
15.1.3 Pin Configuration ................................................................................................ 489
15.1.4 Register Configuration......................................................................................... 489
15.2 Register Descriptions........................................................................................................ 490
15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 490
15.2.2 D/A Control Register (DACR) ............................................................................ 490
15.2.3 D/A Standby Control Register (DASTCR).......................................................... 492
15.3 Operation .......................................................................................................................... 492
15.4 D/A Output Control .......................................................................................................... 494
Section 16 RAM .................................................................................................................. 495
16.1 Overview........................................................................................................................... 495
16.1.1 Block Diagram..................................................................................................... 496
16.1.2 Register Configuration......................................................................................... 496
16.2 System Control Register (SYSCR) ................................................................................... 497
16.3 Operation .......................................................................................................................... 498
Section 17 ROM [H8/3062F-ZTAT R-Mask Version,
On-Chip Masked ROM Models] ............................................................... 499
17.1 Overview........................................................................................................................... 499
17.2 Overview of Flash Memory (H8/3062F-ZTAT R-Mask Version) ................................... 500
17.2.1 Features................................................................................................................ 500
17.2.2 Block Diagram..................................................................................................... 501
17.2.3 Pin Configuration ................................................................................................ 502
17.2.4 Register Configuration......................................................................................... 502
Rev. 6.00 Mar 18, 2005 page xx of xlviii
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