MT6225ACS Просмотр технического описания (PDF) - MediaTek Inc

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MT6225ACS

GSM/GPRS Baseband Processor

MediaTek Inc 

MT6225 GSM/GPRS Baseband Processor Data Sheet Revision 1.00

2.4 Pin Description

Ball

12X12 Name

C2

JTRST#

D2

JTCK

D3

JTDI

E1

JTMS

E2

JTDO

F1

JRTCK

E3

BPI_BUS0

E4

BPI_BUS1

F2

BPI_BUS2

F3

BPI_BUS3

F4

BPI_BUS4

F5

BPI_BUS5

F6

BPI_BUS6

G5

BPI_BUS7

G4

BPI_BUS8

G3

BPI_BUS9

G2

BSI_CS0

G1

BSI_DATA

H1

BSI_CLK

H2

LSCK

H3

LSA0

H4

LSDA

J1

LSCE0#

J2

LSCE1#

J3

LPCE1#

J4

LPCE0#

K1

LRST#

Dir Description

JTAG Port

I JTAG test port reset input

I JTAG test port clock input

I JTAG test port data input

I JTAG test port mode switch

O JTAG test port data output

O JTAG test port returned clock

output

RF Parallel Control Unit

O RF hard-wire control bus 0

O RF hard-wire control bus 1

O RF hard-wire control bus 2

O RF hard-wire control bus 3

O RF hard-wire control bus 4

O RF hard-wire control bus 5

IO RF hard-wire control bus 6

IO RF hard-wire control bus 7

IO RF hard-wire control bus 8

IO RF hard-wire control bus 9

RF Serial Control Unit

O RF 3-wire interface chip select 0

O RF 3-wire interface data output

O RF 3-wire interface clock output

Serial LCD/PM IC Interface

IO Serial display interface data

output

IO Serial display interface address

output

IO Serial display interface clock

output

IO Serial display interface chip

select 0 output

IO Serial display interface chip

select 1 output

Parallel LCD/Nand-Flash

Interface

IO Parallel display interface chip

select 1 output

O Parallel display interface chip

select 0 output

O Parallel display interface Reset

Signal

Mode0

GPIO25

GPIO26

GPIO27

GPIO28

GPIO29

GPIO30

GPIO31

GPIO32

GPIO33

GPIO34

Mode1

Mode2

Mode3

PU Rese IO

/P t

power

D

PD Inpu

t

PU Inpu

t

PU Inpu

t VDD33

PU Inpu

t

PU 0

PU 0

BPI_BUS

6

BPI_BUS

7

BPI_BUS

8

BPI_BUS

9

PWM1 13MHz

PWM2 32KHz

ALERTER 26MHz

BSI_CS1

0

0

0

0

0

0

PD Inpu VDD33

t

PD Inpu

t

PD Inpu

t

PD Inpu

t

0

0 VDD33

0

LSCK

LSA0

LSDA

LSCE0#

LSCE1#

TDMA_C DSP_TID PU Inpu

K

0

t

TDMA_D TDTIRQ PU Inpu

1

t

TDMA_D

0

TCTIRQ2 PU

Inpu

t

VDD33

TDMA_F TCTIRQ1 PU Inpu

S

t

LPCE2# TEVTVA PU Inpu

L

t

LPCE1# NCE1#

PU Inpu VDD33

t

1

1

20

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