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553MLF

LOW SKEW 1 TO 4 CLOCK BUFFER

Integrated Device Technology 

ICS553

LOW SKEW 1 TO 4 CLOCK BUFFER

Pin Assignment

VDD

1

Q0

2

Q1

3

GND

4

8 OE

7 Q3

6 Q2

5 ICLK

8-pin SOIC

FAN OUT BUFFER

Pin Descriptions

Pin

Number

1

2

3

4

5

6

7

8

Pin

Name

VDD

Q0

Q1

GND

ICLK

Q2

Q3

OE

Pin

Type

Power

Output

Output

Power

Input

Output

Output

Input

Pin Description

Connect to +2.5 V, +3.3 V or +5.0 V.

Clock output 0.

Clock output 1.

Connect to ground.

Clock input, 5 V tolerant input.

Clock Output 2.

Clock Output 3.

Output Enable. Tri-states outputs when low. Connect to VDD for normal operation.

External Components

A minimum number of external components are required for proper operation. A decoupling capacitor of

0.01 µF should be connected between VDD on pin 1 and GND on pin 4, as close to the device as possible.

A 33 Ω series terminating resistor may be used on each clock output if the trace is longer than 1 inch.

To achieve the low output skew that the ICS553 is capable of, careful attention must be paid to board

layout. Essentially, all four outputs must have identical terminations, identical loads and identical trace

geometries. If they do not, the output skew will be degraded. For example, using a 30Ω series termination

on one output (with 33Ω on the others) will cause at least 15 ps of skew.

IDT® LOW SKEW 1 TO 4 CLOCK BUFFER

2

ICS553

REV N 051310

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