BD82B65 Просмотр технического описания (PDF) - Intel
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BD82B65 Datasheet PDF : 934 Pages
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14.2
14.3
14.1.7 SCC—Sub Class Code Register (SATA–D31:F2) ..................................... 558
14.1.8 BCC—Base Class Code Register
(SATA–D31:F2SATA–D31:F2) ............................................................. 558
14.1.9 PMLT—Primary Master Latency Timer Register
(SATA–D31:F2) ................................................................................ 559
14.1.10 HTYPE—Header Type Register
(SATA–D31:F2) ................................................................................ 559
14.1.11 PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F2) .................................................................... 559
14.1.12 PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F2) ................................................................................ 560
14.1.13 SCMD_BAR—Secondary Command Block Base Address
Register (SATA D31:F2)..................................................................... 560
14.1.14 SCNL_BAR—Secondary Control Block Base Address
Register (SATA D31:F2)..................................................................... 560
14.1.15 BAR—Legacy Bus Master Base Address Register
(SATA–D31:F2) ................................................................................ 561
14.1.16 ABAR/SIDPBA1—AHCI Base Address Register/Serial ATA
Index Data Pair Base Address (SATA–D31:F2) ...................................... 561
14.1.16.1 When SCC is not 01h ......................................................... 561
14.1.16.2 When SCC is 01h ............................................................... 562
14.1.17 SVID—Subsystem Vendor Identification Register
(SATA–D31:F2) ................................................................................ 562
14.1.18 SID—Subsystem Identification Register (SATA–D31:F2)......................... 562
14.1.19 CAP—Capabilities Pointer Register (SATA–D31:F2) ................................ 562
14.1.20 INT_LN—Interrupt Line Register (SATA–D31:F2) ................................... 563
14.1.21 INT_PN—Interrupt Pin Register (SATA–D31:F2) .................................... 563
14.1.22 IDE_TIM—IDE Timing Register (SATA–D31:F2) ..................................... 563
14.1.23 PID—PCI Power Management Capability Identification
Register (SATA–D31:F2) .................................................................... 563
14.1.24 PC—PCI Power Management Capabilities Register
(SATA–D31:F2) ................................................................................ 564
14.1.25 PMCS—PCI Power Management Control and Status
Register (SATA–D31:F2) .................................................................... 565
14.1.26 MSICI—Message Signaled Interrupt Capability
Identification Register (SATA–D31:F2) ................................................. 566
14.1.27 MSIMC—Message Signaled Interrupt Message
Control Register (SATA–D31:F2) ......................................................... 566
14.1.28 MSIMA— Message Signaled Interrupt Message
Address Register (SATA–D31:F2) ........................................................ 568
14.1.29 MSIMD—Message Signaled Interrupt Message
Data Register (SATA–D31:F2) ............................................................ 568
14.1.30 MAP—Address Map Register (SATA–D31:F2)......................................... 569
14.1.31 PCS—Port Control and Status Register (SATA–D31:F2) .......................... 570
14.1.32 SCLKCG—SATA Clock Gating Control Register ....................................... 572
14.1.33 SCLKGC—SATA Clock General Configuration Register............................. 572
14.1.34 SATACR0—SATA Capability Register 0 (SATA–D31:F2)........................... 573
14.1.35 SATACR1—SATA Capability Register 1 (SATA–D31:F2)........................... 574
14.1.36 FLRCID—FLR Capability ID Register (SATA–D31:F2) .............................. 574
14.1.37 FLRCLV—FLR Capability Length and Version Register
(SATA–D31:F2) ................................................................................ 575
14.1.38 FLRC—FLR Control Register (SATA–D31:F2) ......................................... 575
14.1.39 ATC—APM Trapping Control Register (SATA–D31:F2)............................. 576
14.1.40 ATS—APM Trapping Status Register (SATA–D31:F2) .............................. 576
14.1.41 SP Scratch Pad Register (SATA–D31:F2) .............................................. 576
14.1.42 BFCS—BIST FIS Control/Status Register (SATA–D31:F2)........................ 577
14.1.43 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)..................... 579
14.1.44 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)..................... 579
Bus Master IDE I/O Registers (D31:F2) .............................................................. 580
14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2)....................... 581
14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) ............................ 582
14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F2) ............................................................................. 583
14.2.4 AIR—AHCI Index Register (D31:F2) .................................................... 583
14.2.5 AIDR—AHCI Index Data Register (D31:F2) ........................................... 583
Serial ATA Index/Data Pair Superset Registers .................................................... 584
14.3.1 SINDX—Serial ATA Index Register (D31:F2) ......................................... 584
Datasheet
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