BD82HM67 Просмотр технического описания (PDF) - Intel
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BD82HM67 Datasheet PDF : 934 Pages
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13.2
13.3
13.4
13.5
13.6
13.7
13.8
DMA I/O Registers........................................................................................... 476
13.2.1 DMABASE_CA—DMA Base and Current Address Registers ....................... 477
13.2.2 DMABASE_CC—DMA Base and Current Count Registers.......................... 478
13.2.3 DMAMEM_LP—DMA Memory Low Page Registers ................................... 478
13.2.4 DMACMD—DMA Command Register ..................................................... 479
13.2.5 DMASTA—DMA Status Register ........................................................... 479
13.2.6 DMA_WRSMSK—DMA Write Single Mask Register .................................. 480
13.2.7 DMACH_MODE—DMA Channel Mode Register........................................ 480
13.2.8 DMA Clear Byte Pointer Register ......................................................... 481
13.2.9 DMA Master Clear Register ................................................................. 481
13.2.10 DMA_CLMSK—DMA Clear Mask Register ............................................... 481
13.2.11 DMA_WRMSK—DMA Write All Mask Register ......................................... 482
Timer I/O Registers ......................................................................................... 482
13.3.1 TCW—Timer Control Word Register ..................................................... 483
13.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register ....................... 485
13.3.3 Counter Access Ports Register............................................................. 486
8259 Interrupt Controller (PIC) Registers ........................................................... 486
13.4.1 Interrupt Controller I/O MAP............................................................... 486
13.4.2 ICW1—Initialization Command Word 1 Register .................................... 487
13.4.3 ICW2—Initialization Command Word 2 Register .................................... 488
13.4.4 ICW3—Master Controller Initialization Command
Word 3 Register................................................................................ 488
13.4.5 ICW3—Slave Controller Initialization Command
Word 3 Register................................................................................ 489
13.4.6 ICW4—Initialization Command Word 4 Register .................................... 489
13.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)
Register........................................................................................... 490
13.4.8 OCW2—Operational Control Word 2 Register ........................................ 490
13.4.9 OCW3—Operational Control Word 3 Register ........................................ 491
13.4.10 ELCR1—Master Controller Edge/Level Triggered Register ........................ 492
13.4.11 ELCR2—Slave Controller Edge/Level Triggered Register.......................... 493
Advanced Programmable Interrupt Controller (APIC)............................................ 494
13.5.1 APIC Register Map ............................................................................ 494
13.5.2 IND—Index Register.......................................................................... 494
13.5.3 DAT—Data Register........................................................................... 495
13.5.4 EOIR—EOI Register ........................................................................... 495
13.5.5 ID—Identification Register.................................................................. 496
13.5.6 VER—Version Register ....................................................................... 496
13.5.7 REDIR_TBL—Redirection Table Register ............................................... 497
Real Time Clock Registers................................................................................. 499
13.6.1 I/O Register Address Map .................................................................. 499
13.6.2 Indexed Registers ............................................................................. 500
13.6.2.1 RTC_REGA—Register A ....................................................... 501
13.6.2.2 RTC_REGB—Register B (General Configuration) ..................... 502
13.6.2.3 RTC_REGC—Register C (Flag Register) ................................. 503
13.6.2.4 RTC_REGD—Register D (Flag Register) ................................. 503
Processor Interface Registers ............................................................................ 504
13.7.1 NMI_SC—NMI Status and Control Register ........................................... 504
13.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)
Register........................................................................................... 505
13.7.3 PORT92—Fast A20 and Init Register .................................................... 505
13.7.4 COPROC_ERR—Coprocessor Error Register ........................................... 505
13.7.5 RST_CNT—Reset Control Register ....................................................... 506
Power Management Registers ........................................................................... 507
13.8.1 Power Management PCI Configuration Registers
(PM—D31:F0)................................................................................... 507
13.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0) ................................................................... 508
13.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0) ................................................................... 509
13.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0) ................................................................... 510
13.8.1.4 GEN_PMCON_LOCK—General Power Management
Configuration Lock Register................................................. 514
13.8.1.5 CIR4—Chipset Initialization Register 4 (PM—D31:F0).............. 514
13.8.1.6 BM_BREAK_EN_2 Register #2 (PM—D31:F0)......................... 514
13.8.1.7 BM_BREAK_EN Register (PM—D31:F0) ................................. 515
Datasheet
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