AC Electrical Characteristics
Table 15. Tick Spacing for Memory Controller Signals
PLL Clock Ratio
1:2, 1:3, 1:4, 1:5, 1:6
1:2.5
1:3.5
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
T2
1/4 CLKin
3/10 CLKin
4/14 CLKin
T3
1/2 CLKin
1/2 CLKin
1/2 CLKin
T4
3/4 CLKin
8/10 CLKin
11/14 CLKin
This table is a representation of the information in Table 15.
CLKin
T1
T2
T3
T4
for 1:2, 1:3, 1:4, 1:5, 1:6
CLKin
T1
T2
T3
T4
for 1:2.5
CLKin
for 1:3.5
T1
T2
T3
T4
Figure 12. Internal Tick Spacing for Memory Controller Signals
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
6.3 JTAG Timings
This table lists the JTAG timings.
Table 16. JTAG Timings1
Parameter
Symbol2
Min
Max
Unit
JTAG external clock frequency of operation
fJTG
0
JTAG external clock cycle time
tJTG
30
JTAG external clock pulse width measured at 1.4V
tJTKHKL
15
JTAG external clock rise and fall times
tJTGR and
0
tJTGF
TRST assert time
tTRST
25
Input setup times
Boundary-scan data tJTDVKH
4
TMS, TDI
tJTIVKH
4
33.3
MHz
—
ns
—
ns
5
ns
—
ns
—
ns
—
ns
Notes
—
—
—
6
3, 6
4, 7
4, 7
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2
Freescale Semiconductor
25