CYUSB3035(2013) Просмотр технического описания (PDF) - Cypress Semiconductor
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CYUSB3035 Datasheet PDF : 50 Pages
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CYUSB3035
OTG Connectivity
In OTG mode, FX3S can be configured to be an A, B, or dual-role
device. It can connect to the following:
■ ACA device
■ Targeted USB peripheral
■ SRP-capable USB peripheral
■ HNP-capable USB peripheral
■ OTG host
■ HNP-capable host
■ OTG device
ReNumeration
Because of FX3S's soft configuration, one chip can take on the
identities of multiple distinct USB devices.
When first plugged into USB, FX3S enumerates automatically
with the Cypress Vendor ID (0x04B4) and downloads firmware
and USB descriptors over the USB interface. The downloaded
firmware executes an electrical disconnect and connect. FX3S
enumerates again, this time as a device defined by the
downloaded information. This patented two-step process, called
ReNumeration, happens instantly when the device is plugged in.
EZ-Dtect
FX3S supports USB Charger and accessory detection
(EZ-Dtect). The charger detection mechanism complies with the
Battery Charging Specification Revision 1.1. In addition to
supporting this version of the specification, FX3S also provides
hardware support to detect the resistance values on the ID pin.
FX3S can detect the following resistance ranges:
■ Less than 10 Ω
■ Less than 1 kΩ
■ 65 kΩ to 72 kΩ
■ 35 kΩ to 39 kΩ
■ 99.96 kΩ to 104.4 kΩ (102 kΩ ± 2%)
■ 119 kΩ to 132 kΩ
■ Higher than 220 kΩ
■ 431.2 kΩ to 448.8 kΩ (440 kΩ ± 2%)
FX3S's charger detects a dedicated wall charger, Host/Hub
charger, and Host/Hub.
VBUS Overvoltage Protection
The maximum input voltage on FX3S's VBUS pin is 6 V. A
charger can supply up to 9 V on VBUS. In this case, an external
overvoltage protection (OVP) device is required to protect FX3S
from damage on VBUS. Figure 4 shows the system application
diagram with an OVP device connected on VBUS. Refer to
Table 7 for the operating range of VBUS and VBATT.
Figure 4. System Diagram with OVP Device For VBUS
POWER SUBSYSTEM
1
OVP device
2
3
4
5
6
7
8
9 GND
VBUS
OTG_ID
SSRX-
SSRX+
SSTX-
SSTX+
D-
D+
EZ-USB FX3S
Carkit UART Mode
The USB interface supports the Carkit UART mode (UART over
D+/D–) for non-USB serial data transfer. This mode is based on
the CEA-936A specification.
In the Carkit UART mode, the output signaling voltage is 3.3 V.
When configured for the Carkit UART mode, TXD of UART
(output) is mapped to the D– line, and RXD of UART (input) is
mapped to the D+ line.
In the Carkit UART mode, FX3S disables the USB transceiver
and D+ and D– pins serve as pass-through pins to connect to the
UART of the host processor. The Carkit UART signals may be
routed to the GPIF II interface or to GPIO[48] and GPIO[49], as
shown in Figure 5 on page 6.
In this mode, FX3S supports a rate of up to 9600 bps.
Document Number: 001-84160 Rev. *B
Page 5 of 50
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