CYUSB3033(2013) Просмотр технического описания (PDF) - Cypress Semiconductor
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CYUSB3033 Datasheet PDF : 50 Pages
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CYUSB3035
Functional Overview
Cypress’s EZ-USB FX3S is the next-generation USB 3.0
peripheral controller, providing integrated and flexible features.
FX3S has a fully configurable, parallel, general programmable
interface called GPIF II, which can connect to any processor,
ASIC, or FPGA. GPIF II is an enhanced version of the GPIF in
FX2LP, Cypress’s flagship USB 2.0 product. It provides easy and
glueless connectivity to popular interfaces, such as
asynchronous SRAM, asynchronous and synchronous address
data multiplexed interfaces, and parallel ATA. FX3S has
integrated the USB 3.0 and USB 2.0 physical layers (PHYs)
along with a 32-bit ARM926EJ-S microprocessor for powerful
data processing and for building custom applications. It
implements an architecture that enables 185-MBps data transfer
from GPIF II to the USB interface.
FX3S features an integrated storage controller and can support
up to two independent mass storage devices on its storage ports.
It can support SD 3.0 and eMMC 4.41 memory cards. It can also
support SDIO on these ports.
An integrated USB 2.0 OTG controller enables applications in
which FX3S may serve dual roles; for example, EZ-USB FX3S
may function as an OTG Host to MSC as well as HID-class
devices. FX3S contains 512 KB or 256 KB of on-chip SRAM for
code and data. EZ-USB FX3S also provides interfaces to
connect to serial peripherals such as UART, SPI, I2C, and I2S.
FX3S comes with application development tools. The software
development kit comes with application examples for
accelerating time to market.
FX3S complies with the USB 3.0 v1.0 specification and is also
backward compatible with USB 2.0. It also complies with the
Battery Charging Specification v1.1 and USB 2.0 OTG
Specification v2.0.
Application Examples
In a typical application (see Figure 1), FX3S functions as a
coprocessor and connects to an external processor, which
manages system-level functions. Figure 2 shows a typical appli-
cation diagram when FX3S functions as the main processor.
Figure 1. EZ-USB FX3S as a Coprocessor
Note
1. Assuming that GPIF II is configured for a 16-bit data bus (available with certain part numbers; see Ordering Information on page 48), synchronous interface operating
at 100 MHz. This number also includes protocol overheads.
Document Number: 001-84160 Rev. *B
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