PIC24HJ128GP202 Просмотр технического описания (PDF) - Microchip Technology

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PIC24HJ128GP202

High-Performance, 16-bit Microcontrollers

Microchip Technology 

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

3.0 CPU

Note 1: This data sheet summarizes the features

of

the

PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04

and

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to Section 2. “CPU” (DS70245) of

the “dsPIC33F/PIC24H Family Reference

Manual”, which is available from the

Microchip website (www.microchip.com).

2: Some registers and associated bits

described in this section may not be avail-

able on all devices. Refer to Section 4.0

“Memory Organization” in this data

sheet for device-specific register and bit

information.

3.1 Overview

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 CPU module has a 16-bit

(data) modified Harvard architecture with an enhanced

instruction set and addressing modes. The CPU has a

24-bit instruction word with a variable length opcode

field. The Program Counter (PC) is 23 bits wide and

addresses up to 4M x 24 bits of user program memory

space. The actual amount of program memory

implemented varies by device. A single-cycle

instruction prefetch mechanism is used to help

maintain throughput and provides predictable

execution. All instructions execute in a single cycle,

with the exception of instructions that change the

program flow, the double word move (MOV.D)

instruction and the table instructions. Overhead-free,

single-cycle program loop constructs are supported

using the REPEAT instruction, which is interruptible at

any point.

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 devices have sixteen,

16-bit working registers in the programmer’s model.

Each of the working registers can serve as a data,

address or address offset register. The 16th working

register (W15) operates as a software Stack Pointer

(SP) for interrupts and calls.

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 instruction set includes

many addressing modes and is designed for optimum

C compiler efficiency. For most instructions, the

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 is capable of executing a data

(or program data) memory read, a working register

(data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, three parameter instructions can be supported,

allowing A + B = C operations to be executed in a single

cycle.

A block diagram of the CPU is shown in Figure 3-1, and

the programmer’s model for the PIC24HJ32GP302/

304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/

X04 is shown in Figure 3-2.

3.2 Data Addressing Overview

The data space can be linearly addressed as 32K words

or 64 Kbytes using an Address Generation Unit (AGU).

The upper 32 Kbytes of the data space memory map can

optionally be mapped into program space at any 16K pro-

gram word boundary defined by the 8-bit Program Space

Visibility Page (PSVPAG) register. The program to data

space mapping feature lets any instruction access pro-

gram space as if it were data space.

The data space also includes 2 Kbytes of DMA RAM,

which is primarily used for DMA data transfers, but may

be used as general purpose RAM.

© 2009 Microchip Technology Inc.

Preliminary

DS70293D-page 19

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