DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

DF8064101211300SR0VY Просмотр технического описания (PDF) - Intel

Номер в каталоге
Компоненты Описание
производитель
DF8064101211300SR0VY Datasheet PDF : 122 Pages
First Prev 111 112 113 114 115 116 117 118 119 120 Next Last
7.3.2
7.3.2.1
7.3.2.2
7.3.2.3
DRAM Power Management and Initialization
The processor implements extensive support for power management on the SDRAM
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals, which the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.
Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that has its level is recognized
(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the
DDR controller to make sure the SDRAM components float DQ and DQS during
powerup.
CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is guaranteed to remain inactive for
much longer than the specified 200 micro-seconds after power and clocks to SDRAM
devices are stable.
Conditional Self-Refresh
Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory into
self-refresh in the package C3 and C6 low-power states. RMPM functionality depends
on graphics/display state (relevant only when internal graphics is being used), as well
as memory traffic patterns generated by other connected I/O devices.
When entering the Suspend-to-RAM (STR) state, the processor core flushes pending
cycles and then enters all SDRAM ranks into self refresh. In STR, the CKE signals
remain LOW so the SDRAM devices perform self-refresh.
The target behavior is to enter self-refresh for the package C3 and C6 states as long as
there are no memory requests to service.
Dynamic Power Down Operation
Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices in a power down state.The
processor core controller can be configured to put the devices in active power down
(CKE deassertion with open pages) or precharge power down (CKE deassertion with all
pages closed). Precharge power down provides greater power savings but has a bigger
performance impact, since all pages will first be closed before putting the devices in
power down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
Datasheet - Volume 1 of 2
111

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]