CYUSB3013 Просмотр технического описания (PDF) - Cypress Semiconductor
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CYUSB3013 Datasheet PDF : 54 Pages
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CYUSB301X/CYUSB201X
GPIF II
The high-performance GPIF II interface enables functionality
similar to, but more advanced than, FX2LP’s GPIF and Slave
FIFO interfaces.
The GPIF II is a programmable state machine that enables a
flexible interface that may function either as a master or slave in
industry-standard or proprietary interfaces. Both parallel and
serial interfaces may be implemented with GPIF II.
Here is a list of GPIF II features:
■ Functions as master or slave
■ Provides 256 firmware programmable states
■ Supports 8-bit, 16-bit, 24-bit, and 32-bit parallel data bus
■ Enables interface frequencies up to 100 MHz
■ Supports 14 configurable control pins when a 32- bit data bus
is used. All control pins can be either input/output or bidirec-
tional.
■ Supports 16 configurable control pins when a 16/8 data bus is
used. All control pins can be either input/output or bi-directional.
GPIF II state transitions are based on control input signals. The
control output signals are driven as a result of the GPIF II state
transitions. The INT# output signal can be controlled by GPIF II.
Refer to the GPIFII Designer tool. The GPIF II state machine’s
behavior is defined by a GPIF II descriptor. The GPIF II
descriptor is designed such that the required interface specifica-
tions are met. 8 KB of memory (separate from the 256/512 KB of
embedded SRAM) is dedicated to the GPIF II waveform where
the GPIF II descriptor is stored in a specific format.
Cypress’s GPIFII Designer Tool enables fast development of
GPIF II descriptors and includes examples for common
interfaces.
Example implementations of GPIF II are the asynchronous slave
FIFO and synchronous slave FIFO interfaces.
Slave FIFO interface
The Slave FIFO interface signals are shown in Figure 5. This
interface allows an external processor to directly access up to
four buffers internal to FX3. Further details of the Slave FIFO
interface are described on page 24.
Note Access to all 32 buffers is also supported over the slave
FIFO interface. For details, contact Cypress Applications
Support.
Figure 5. Slave FIFO Interface
SLCS#
PKTEND
External Master
(For example,
M C U /C P U /
F P G A /A S IC )
FLAGB
FLAGA
A [1 :0 ]
D[31:0]
SLWR#
EZ-USB FX3
SLRD#
SLOE#
CPU
FX3 has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU.
The core has direct access to 16 KB of Instruction Tightly
Coupled Memory (TCM) and 8 KB of Data TCM. The
ARM926EJ-S core provides a JTAG interface for firmware
debugging.
FX3 offers the following advantages:
■ Integrates 256/512 KB of embedded SRAM for code and data
and 8 KB of Instruction cache and Data cache.
■ Implements efficient and flexible DMA connectivity between the
various peripherals (such as, USB, GPIF II, I2S, SPI, UART,
I2C), requiring firmware only to configure data accesses
between peripherals, which are then managed by the DMA
fabric.
■ Allows easy application development using industry-standard
development tools for ARM926EJ-S.
Examples of the FX3 firmware are available with the Cypress
EZ-USB FX3 Development Kit.
JTAG Interface
FX3’s JTAG interface has a standard five-pin interface to connect
to a JTAG debugger in order to debug firmware through the
CPU-core's on-chip-debug circuitry.
Industry-standard debugging tools for the ARM926EJ-S core
can be used for the FX3 application development.
Other Interfaces
FX3 supports the following serial peripherals:
■ SPI
■ UART
■ I2C
■ I2S
The SPI, UART, and I2S interfaces are multiplexed on the serial
peripheral port.
The CYUSB3012 and CYUSB3014 Pin List on page 15 shows
details of how these interfaces are multiplexed. Note that when
GPIF II is configured for a 32-bit data bus width (CYUSB3012
and CYUSB3014), then the SPI interface is not available.
SPI Interface
FX3 supports an SPI Master interface on the Serial Peripherals
port. The maximum operation frequency is 33 MHz.
The SPI controller supports four modes of SPI communication
(see SPI Timing Specification on page 40 for details on the
modes) with the Start-Stop clock. This controller is a
single-master controller with a single automated SSN control. It
supports transaction sizes ranging from four bits to 32 bits.
Note: Multiple Flags may be configured.
Document Number: 001-52136 Rev. *U
Page 8 of 54
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