CYUSB3011 Просмотр технического описания (PDF) - Cypress Semiconductor

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CYUSB3011

EZ-USB® FX3: SuperSpeed USB Controller

Cypress Semiconductor 

CYUSB301X/CYUSB201X

Power

FX3 has the following power supply domains:

■ IO_VDDQ: This is a group of independent supply domains for

digital I/Os. The voltage level on these supplies is 1.8 V to 3.3 V.

FX3 provides six independent supply domains for digital I/Os

listed as follows (see Table 7 on page 15 for details on each of

the power domain signals):

❐ VIO1: GPIF II I/O

❐ VIO2: IO2

❐ VIO3: IO3

❐ VIO4: UART-/SPI/I2S

❐ VIO5: I2C and JTAG (supports 1.2 V to 3.3 V)

❐ CVDDQ: This is the supply voltage for clock and reset I/O. It

should be either 1.8 V or 3.3 V based on the voltage level of

the CLKIN signal.

❐ VDD: This is the supply voltage for the logic core. The nominal

supply-voltage level is 1.2 V. This supplies the core logic

circuits. The same supply must also be used for the following:

• AVDD: This is the 1.2-V supply for the PLL, crystal oscilla-

tor, and other core analog circuits

• U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt-

ages for the USB 3.0 interface.

■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply

for the USB I/O and analog circuits. This supply powers the

USB transceiver through FX3's internal voltage regulator.

VBATT is internally regulated to 3.3 V.

Power Modes

FX3 supports the following power modes:

■ Normal mode: This is the full-functional operating mode. The

internal CPU clock and the internal PLLs are enabled in this

mode.

❐ Normal operating power consumption does not exceed the

sum of ICC Core max and ICC USB max (see Table 7 on page

15 for current consumption specifications).

❐ The I/O power supplies VIO2, VIO3, VIO4, and VIO5 can be

turned off when the corresponding interface is not in use.

VIO1 cannot be turned off at any time if the GPIF II interface

is used in the application.

■ Low-power modes (see Table 6 on page 11):

❐ Suspend mode with USB 3.0 PHY enabled (L1)

❐ Suspend mode with USB 3.0 PHY disabled (L2)

❐ Standby mode (L3)

❐ Core power-down mode (L4)

Table 6. Entry and Exit Methods for Low-Power Modes

Low-Power Mode

Characteristics

Methods of Entry

Methods of Exit

Suspend Mode with ■ The power consumption in this mode does ■ Firmware executing on

■ D+ transitioning to low

USB 3.0 PHY

Enabled (L1)

not exceed ISB1

ARM926EJ-S core can put FX3 into or high

suspend mode. For example, on

■ USB 3.0 PHY is enabled and is in U3 mode USB suspend condition, firmware ■ D- transitioning to low

(one of the suspend modes defined by the may decide to put FX3 into suspend or high

USB 3.0 specification). This one block

mode

alone is operational with its internal clock

■ Impedance change on

while all other clocks are shut down

■ External Processor, through the use OTG_ID pin

■ All I/Os maintain their previous state

of mailbox registers, can put FX3 into ■ Resume condition on

suspend mode

SSRX±

■ Power supply for the wakeup source and

core power must be retained. All other

■ Detection of VBUS

power domains can be turned on/off

individually

■ Level detect on

UART_CTS

■ The states of the configuration registers,

buffer memory, and all internal RAM are

(programmable

polarity)

maintained

■ GPIF II interface

■ All transactions must be completed before

assertion of CTL[0]

FX3 enters Suspend mode (state of

outstanding transactions are not

■ Assertion of RESET#

preserved)

■ The firmware resumes operation from

where it was suspended (except when

woken up by RESET# assertion) because

the program counter does not reset

Document Number: 001-52136 Rev. *U

Page 11 of 54

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