AD1846 Просмотр технического описания (PDF) - Analog Devices

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AD1846

Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec

Analog Devices 

AD1846

Interface Configuration Register (IXA3:0 = 9)

IXA3:0

9

Data 7

CPIO

Data 6

PPIO

Data 5

res

Data 4

res

Data 3

ACAL

Data 2

SDC

Data 1

CEN

Data 0

PEN

The contents of the Interface Configuration Register cannot be changed except when the AD1846 is in Mode Change Enable (MCE) state.

Write attempts to this register when the AD1846 is not in the MCE state will not be successful. PEN and CEN are exceptions; these bits may al-

ways be written.

PEN

Playback Enable. This bit will enable the playback of data in the format selected. The AD1846 will generate PDRQ and

respond to PDAK signals when this bit is enabled and PPIO = 0. If PPIO = 1, this bit enables Programmed I/O (PIO)

playback mode. PEN may be set and reset without setting the MCE bit.

0

Playback disabled (PDRQ and PIO Playback Data Register inactive)

1

Playback enabled

CEN

Capture Enable. This bit will enable the capture of data in the format selected. The AD1846 will generate CDRQ and re-

spond to CDAK signals when this bit is enabled and CPIO = 0. If CPIO = 1, this bit enables PIO capture mode. CEN

may be set and reset without setting the MCE bit.

0

Capture disabled (CDRQ and PIO Capture Data Register inactive)

1

Capture enabled

SDC

Single DMA Channel. This bit will force both capture and playback DMA requests to occur on the Playback DMA chan-

nel. The Capture DMA CDRQ pin will be LO. This bit will allow the AD1846 to be used with only one DMA channel.

Simultaneous capture and playback cannot occur in this mode. Should both capture and playback be enabled

(CEN = PEN = 1) in the mode, only playback will occur. See “Data and Control Transfers” for further explanation.

0

Dual DMA channel mode

1

Single DMA channel mode

ACAL

Autocalibrate Enable. This bit determines whether the AD1846 performs an autocalibrate whenever the PWRDWN pin is

deasserted or from the Mode Change Enable (MCE) bit being reset. ACAL is normally set. See “Autocalibration” below

for a description of a complete autocalibration sequence.

0

No autocalibration

1

Autocalibration after power down/reset or mode change

res

Reserved for future expansion. Always write zeros to these bits.

PPIO Playback PIO Enable. This bit determines whether the playback data is transferred via DMA or PIO.

0

DMA transfers only

1

PIO transfers only

CPIO Capture PIO Enable. This bit determines whether the capture data is transferred via DMA or PIO.

0

DMA transfers only

1

PIO transfers only

This register’s initial state after reset is “00xx 1000.”

Pin Control Register (IXA3:0 = 10)

IXA3:0

10

Data 7

XCTL1

Data 6

XCTL0

Data 5

res

Data 4

res

Data 3

res

Data 2

res

Data 1

IEN

Data 0

res

res

Reserved for future expansion. Always write zeros to these bits.

IEN

Interrupt Enable. This bit enables the interrupt pin. The Interrupt Pin will go active HI when the number of samples pro-

grammed in the Base Count Register is reached.

0

Interrupt disabled

1

Interrupt enabled

XCTL1:0 External Control. The state of these independent bits is reflected on the respective XCTL1:0 pins of the AD1846.

0

TTL Logic LO on XCTL1:0 pins

1

TTL Logic HI on XCTL1:0 pins

This register’s initial state after reset is “00xx xx0x.”

–18–

REV. A

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