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V363EPC Просмотр технического описания (PDF) - QuickLogic Corporation

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V363EPC Datasheet PDF : 23 Pages
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Serial EEPROM Port TImings
5.3 Serial EEPROM Port TImings
The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms generated are
shown in Figure 8.
Figure 8: Serial EEPROM Waveforms and Timings
START CONDITION
512 PCI Bus Clocks
STOP CONDITION
SCL
SDA
256 PCI Bus Clocks
256 PCI Bus Clocks
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V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
© 2000 V3 Semiconductor Corp.

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