H3LIS331DLTR Просмотр технического описания (PDF) - STMicroelectronics
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H3LIS331DLTR Datasheet PDF : 38 Pages
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Mechanical and electrical specifications
H3LIS331DL
2.3.2
I2C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Symbol
Table 6. I2C slave timing values
Parameter
I2C standard mode (1)
Min.
Max.
I2C fast mode (1)
Min.
Max.
f(SCL)
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
tr(SDA) tr(SCL)
tf(SDA) tf(SCL)
th(ST)
tsu(SR)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition
setup time
0
4.7
4.0
250
0.01
4
4.7
100
0
400
1.3
0.6
100
3.45
0.01
0.9
1000
20 + 0.1Cb (2)
300
300
20 + 0.1Cb (2)
300
0.6
0.6
tsu(SP)
STOP condition setup time
4
0.6
tw(SP:SR)
Bus free time between STOP
and START condition
4.7
1.3
1. Data based on standard I2C protocol requirement, not tested in production.
2. Cb = total capacitance of one bus line, in pF.
Figure 4. I2C slave timing diagram
Unit
KHz
μs
ns
μs
ns
μs
START
SDA
tf(SD A)
tr(SDA)
SCL
tsu(SDA)
th(SDA)
REPEATED
START
tsu(SR)
tw (SP:SR)
START
tsu(SP)
STO P
th(ST) tw (SCLL)
tw (SCLH)
tr(SCL)
tf(SCL)
Note:
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
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DocID023111 Rev 3
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