ADN4695EBRZ(RevA) Просмотр технического описания (PDF) - Analog Devices

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ADN4695EBRZ
(Rev.:RevA)

3.3 V, 100 Mbps, Half- and Full-Duplex, High Speed M-LVDS Transceivers

Analog Devices 

Data Sheet

RECEIVER TIMING MEASUREMENTS

A

RO

VID

B RE

CL

15pF

VOUT

NOTES

1. CL IS 20%, CERAMIC, SURFACE MOUNT, AND

INCLUDES PROBE/STRAY CAPACITANCE

< 2cm FROM DUT.

Figure 29. Receiver Timing Measurement

1.4V

S1

1.0V

1.2V

RE INPUT

A

RO

B RE

CL

15pF

RL

499Ω

VOUT

VTEST

NOTES

1. CL IS 20% AND INCLUDES PROBE/STRAY

CAPACITANCE < 2cm FROM DUT.

2. RL IS 1% METAL FILM, SURFACE MOUNT, <2cm FROM DUT.

Figure 30. Receiver Enable/Disable Time

INPUT

(VA – VB)

1/f0

VOH

OUTPUT

(IDEAL)

VOL

0.5VCC

1/f0

0.5VCC

VOH

OUTPUT

(ACTUAL)

VOL

0.5VCC

tc(n)

tJ(PER) = |tc(n) – 1/f0|

0.5VCC

NOTES

1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;

50MHz; 50% ± 1% DUTY CYCLE.

2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.

Figure 31. Receiver Period Jitter Characteristics

ADN4690E/ADN4692E/ADN4694E/ADN4695E

VA

VB

VID

0V

0V

tRPHL

tRPLH

VOH

90%

90%

VOUT

VOL

VCC/2

10%

tF

VCC/2

10%

tR

NOTES

1. INPUT PULSE GENERATOR: 1MHz; 50% ± 5% DUTY CYCLE; tR, tF ≤ 1ns.

2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.

Figure 32. Receiver Propagation and Rise/Fall Times

VCC

RE INPUT

VOUT

(VTEST = VCC)

(A = 1V)

VOUT

(VTEST = 0V)

(A = 1.4V)

0.5VCC

tRPZL

0.5VCC

tRPZH

0.5VCC

0.5VCC

tRPLZ

0V

VCC

tRPHZ

VOL + 0.5V

VOL

VOH

VOH – 0.5V

0V

NOTES

1. INPUT PULSE GENERATOR: 1MHz; 50 ± 5% DUTY CYCLE; tR, tF ≤ 1ns.

Figure 33. Receiver Enable/Disable Times

VA

INPUT

(PRBS)

VB

VOH

OUTPUT

VOL

VCC/2

tJ(PP)

VCC/2

NOTES

1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;

100Mbps; 215 – 1PRBS.

2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.

Figure 34. Receiver Peak-to-Peak Jitter Characteristics

Rev. A | Page 13 of 20

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