ADN4690E(RevA) Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
ADN4690E
(Rev.:RevA)
(Rev.:RevA)
Analog Devices
ADN4690E Datasheet PDF : 20 Pages
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ADN4690E/ADN4692E/ADN4694E/ADN4695E
Data Sheet
DRIVER TIMING MEASUREMENTS
A/Y
DI
C1
1pF
C3
R1
0.5pF OUT 50Ω
B/Z
C2
1pF
NOTES
1. C1, C2, AND C3 ARE 20% AND INCLUDE PROBE/STRAY
CAPACITANCE < 2cm FROM DUT.
2. R1 IS 1%, METAL FILM, SURFACE MOUNT,
<2cm FROM DUT.
Figure 23. Driver Timing Measurement
VCC
A/Y
S1
DI
DE B/Z
C1
R1
1pF
C4
24.9Ω
0.5pF OUT
R2
24.9Ω
C2
1pF
C3
2.5pF
NOTES
1. C1, C2, C3, AND C4 ARE 20% AND INCLUDE PROBE/STRAY
CAPACITANCE < 2cm FROM DUT.
2. R1 AND R2 ARE 1%, METAL FILM, SURFACE MOUNT,
<2cm FROM DUT.
Figure 24. Driver Enable/Disable Time Test Circuit
VCC
INPUT
(CLOCK)
VCC/2
0V
1/f0
VCC/2
OUTPUT
VA – VB
OR
0V
0V
VY – VZ
(IDEAL)
1/f0
OUTPUT
VA – VB
OR
0V
0V
VY – VZ
(ACTUAL)
tc(n)
tJ(PER) = |tc(n) – 1/f0|
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
50MHz; 50% ± 1% DUTY CYCLE.
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
Figure 25. Driver Period Jitter Characteristics
VCC
DI
0V
VSS
OUT
VCC/2
tPLH
90% VSS
0V
VCC/2
tPHL
90% VSS
0V
VPH
10% VSS
0% VSS
tR
10% VSS
VPL
tF
NOTES
1. INPUT PULSE GENERATOR: 1MHz; 50% ± 5% DUTY CYCLE; tR, tF ≤ 1ns.
2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
Figure 26. Driver Propagation, Rise/Fall Times and Voltage Overshoot
VCC
DE
0.5VCC
tPZL
0.5VCC
0V
tPLZ
0V
OUT
(DI = 0V)
OUT
(DI = VCC)
–0.1V
tPZH
0.1V
–0.1V
tPHZ
0.1V
~ –0.6V
~ +0.6V
0V
NOTES
1. INPUT PULSE GENERATOR: 1MHz; 50% ± 5% DUTY CYCLE; tR, tF ≤ 1ns.
2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
Figure 27. Driver Enable/Disable Times
VCC
INPUT
(PRBS)
0V
VA – VB
OR
VY – VZ
OUTPUT
VA – VB
OR
VY – VZ
VCC/2
0V
tJ(PP)
VCC/2
0V
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
100Mbps; 215 – 1PRBS.
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
Figure 28. Driver Peak-to-Peak Jitter Characteristics
Rev. A | Page 12 of 20
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