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CY7C1371D-100BZXC

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1371D

CY7C1373D

Document History Page

Document Title: CY7C1371D/CY7C1373D 18-Mbit (512K x 36/1 Mbit x 18) Flow-Through SRAM with NoBL™ Architecture

Document Number: 38-05556

Orig. of

REV. ECN NO. Issue Date Change

Description of Change

** 254513 See ECN RKF New data sheet

*A 288531 See ECN

SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

non-compliance with 1149.1

Removed 117 Mhz Speed Bin

Added lead-free information for 100-Pin TQFP , 119 BGA and 165 FBGA

Packages

Added comment of ‘Lead-free BG packages availability’ below the Ordering Infor-

mation

Document #: 38-05556 Rev. *A

Page 30 of 30

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