FSL4110LRLX Просмотр технического описания (PDF) - Fairchild Semiconductor
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FSL4110LRLX Datasheet PDF : 15 Pages
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IDS
several
mseconds
tS = 1/fS
mode. Additionally to reduce the audible noise soft-
burst is implemented.
VO
tS
Dt
t
fSW
fS + 1/2DfSMAX
several
miliseconds
no repetition
fS - 1/2DfSMAX
t
Figure 27. Frequency Fluctuation Waveforms
5. Soft-Start
The internal soft-start circuit slowly increases the
SenseFET current after it starts. The typical soft-start
time is 20 ms, as shown in Figure 28, where
progressive increments of the SenseFET current are
allowed during startup. The pulse width to the power
switching device is progressively increased to establish
the correct working conditions for transformers,
inductors, and capacitors. The voltage on the output
capacitors is gradually increased to smoothly establish
the required output voltage. Soft-start also helps to
prevent transformer saturation and reduces stress on
the secondary diode.
2.5ms
ILIM
Soft start envelope
Drain Current
8-Steps
t
t
VFB
0.5V
0.4V
t
IDS
t
VDS
t
Switching
disabled
Switching
disabled
Figure 29. Burst Mode Operation
7. Line Compensation
All of switching devices have their own inherent
propagation delays. This propagation delay will cause a
current limit delay defined as tCLD. Because there is a
current limit delay, tCLD, there is a difference in the
current peak between low and high input voltage. The
variance in the current peak is related to the difference
between the input voltages, a wider gap in input voltage
will result in a greater variance of the current peak.
In order to have a constant current peak regardless of
the input voltage, line compensation is required.
FSL4110LR has line compensation, so the real peak
value of high input voltage is similar to that of low input
voltage. tCLD effect could be neglected as showed
Figure 30.
Figure 28. Internal Soft-Start
6. Burst Mode Operation
To minimize power dissipation in standby mode, the
FSL4110LR enters burst mode. As the load decreases,
the feedback voltage decreases. The device
automatically enters burst mode when the feedback
voltage drops below VBURL (400 mV), as shown in
Figure 29. At this point, switching stops and the output
voltages start to drop at a rate dependent on standby
current load. This causes the feedback voltage to rise.
Once it passes VBURH (500 mV), switching resumes.
Feedback voltage then falls and the process repeats.
Burst Mode alternately enables and disables switching
of the SenseFET, reducing switching loss in standby
IDRAIN(85 VAC): 100 mA/div
IDRAIN(460 VAC): 100 mA/div
500 ns/div
Figure 30. ILIMIT Waveforms (85 VAC vs. 460 VAC)
© 2014 Fairchild Semiconductor Corporation
FSL4110LR • Rev. 1.3
12
www.fairchildsemi.com
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