AT91SAM9G25-CU(2013) Просмотр технического описания (PDF) - Atmel Corporation

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Компоненты Описание

производитель

AT91SAM9G25-CU
(Rev.:2013)

AT91SAM ARM-based Embbedded MPU

Atmel Corporation 

4.5 247-ball BGA Package Pinout

Table 4-4 provides the pin description of 247-ball TFBGA and 247-ball VFBGA packages.

Table 4-4. Pin Description BGA247

Primary

Ball Power Rail I/O Type

Signal

Dir

P2

VDDIOP0

GPIO

PA0

I/O

P3

VDDIOP0

GPIO

PA1

I/O

M7

VDDIOP0

GPIO

PA2

I/O

T2

VDDIOP0

GPIO

PA3

I/O

N5

VDDIOP0

GPIO

PA4

I/O

V1

VDDIOP0

GPIO

PA5

I/O

U2

VDDIOP0

GPIO

PA6

I/O

W1

VDDIOP0

GPIO

PA7

I/O

N6

VDDIOP0

GPIO

PA8

I/O

P5

VDDIOP0

GPIO

PA9

I/O

V2

VDDIOP0

GPIO

PA10

I/O

R2

VDDIOP0

GPIO

PA11

I/O

W2

VDDIOP0

GPIO

PA12

I/O

V3

VDDIOP0 GPIO_CLK

PA13

I/O

T3

VDDIOP0

GPIO

PA14

I/O

U3

VDDIOP0

GPIO

PA15

I/O

R3

VDDIOP0

GPIO

PA16

I/O

R5

VDDIOP0 GPIO_CLK

PA17

I/O

V5

VDDIOP0

GPIO

PA18

I/O

U4

VDDIOP0

GPIO

PA19

I/O

U5

VDDIOP0

GPIO

PA20

I/O

V4

VDDIOP0

GPIO

PA21

I/O

R6

VDDIOP0

GPIO

PA22

I/O

P6

VDDIOP0 GPIO_CLK

PA23

I/O

P7

VDDIOP0

GPIO

PA24

I/O

R7

VDDIOP0

GPIO

PA25

I/O

U6

VDDIOP0

GPIO

PA26

I/O

L9

VDDIOP0

GPIO

PA27

I/O

V6

VDDIOP0

GPIO

PA28

I/O

U7

VDDIOP0

GPIO

PA29

I/O

V7

VDDIOP0

GPIO

PA30

I/O

U8

VDDIOP0

GPIO

PA31

I/O

F5

VDDANA

GPIO

PB0

I/O

G6

VDDANA

GPIO

PB1

I/O

E3

VDDANA

GPIO

PB2

I/O

E2

VDDANA

GPIO

PB3

I/O

D2

VDDANA GPIO_CLK

PB4

I/O

F3

VDDANA

GPIO

PB5

I/O

Alternate

PIO Peripheral A

Signal

Dir

Signal

Dir

TXD0

O

RXD0

I

RTS0

O

CTS0

I

SCK0

I/O

TXD1

O

RXD1

I

TXD2

O

RXD2

I

DRXD

I

DTXD

O

SPI0_MISO I/O

SPI0_MOSI I/O

SPI0_SPCK I/O

SPI0_NPCS0 I/O

MCI0_DA0 I/O

MCI0_CDA I/O

MCI0_CK I/O

MCI0_DA1 I/O

MCI0_DA2 I/O

MCI0_DA3 I/O

TIOA0

I/O

TIOA1

I/O

TIOA2

I/O

TCLK0

I

TCLK1

I

TCLK2

I

TIOB0

I/O

TIOB1

I/O

TIOB2

I/O

TWD0

I/O

TWCK0

O

ERX0

I

ERX1

I

ERXER

I

ERXDV

I

ETXCK

I

EMDIO

I/O

PIO Peripheral B

Signal

Dir

SPI1_NPCS1 O

SPI0_NPCS2 O

MCI1_DA1 I/O

MCI1_DA2 I/O

MCI1_DA3 I/O

SPI0_NPCS1 O

SPI1_NPCS0 I/O

MCI1_DA0 I/O

MCI1_CDA I/O

MCI1_CK

I/O

SPI1_MISO I/O

SPI1_MOSI I/O

SPI1_SPCK I/O

TK

I/O

TF

I/O

TD

O

RD

I

RK

I/O

RF

I/O

SPI1_NPCS3 O

SPI1_NPCS2 O

RTS2

O

CTS2

I

SCK2

I/O

SPI0_NPCS3 O

TWD2

I/O

TWCK2

O

PIO Peripheral C Reset State

Signal

Signal, Dir,

Dir PU, PD, ST

PIO, I, PU, ST

PIO, I, PU, ST

ETX0

O PIO, I, PU, ST

ETX1

O PIO, I, PU, ST

ETXER

O PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

EMDC

O PIO, I, PU, ST

ETXEN

O PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

PIO, I, PU, ST

SAM9G25 [DATASHEET] 19

11032C–ATARM–25-Jan-13

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