AT91SAM9G46B-CU Просмотр технического описания (PDF) - Atmel Corporation

Номер в каталоге

Компоненты Описание

производитель

AT91SAM9G46B-CU

SMART ARM-based Embedded MPU

Atmel Corporation 

4.2.1 Power-up Sequence

Figure 4-1. VDDCORE and VDDIO Constraints at Startup

VDD (V)

VDDIOtyp

VOH

VIH

VDDCOREtyp

VT+

VDDIO

VDDIO > VOH

VDDIO > VIH

VDDCORE

Core Supply POR Output

SLCK

t

<---- tRST ---> <- t1 -> <------------ t2 ----------->

VDDCORE and VDDBU are controlled by the internal PORs (Power-on Reset) to guarantee that these power sources

reach their target values prior to the release of POR.

 VDDIOP must be ≥ VIH (refer to Table 48-2 “DC Characteristics” for more details) within (tRST + t1) after

VDDCORE has reached VT+

 VDDIOM must reach VOH (refer to Table 48-2 “DC Characteristics” for more details) within (tRST + t1 + t2) after

VDDCORE has reached VT+

̶ tRST is a POR characteristic

̶ t1 = 3 × tSLCK

̶ t2 = 16 × tSLCK

The tSLCK min (22 µs) is obtained for the maximum frequency of the internal RC oscillator (44 kHz).

̶ tRST = 30 µs

̶ t1 = 66 µs

̶ t2 = 352 µs

In conclusion, VDDIOP and VDDIOM must be established first, then VDDCORE to ensure a reliable operation of the

device. VDDOSC, VDDPLL, VDDUTMII and VDDUTMIC must be started at any time prior to VDDCORE to ensure correct

behavior of the ROM code.

SAM9G46 Series [DATASHEET]

15

Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15

Share Link: