AT91SAM9263(2009) Просмотр технического описания (PDF) - Atmel Corporation

Номер в каталоге

Компоненты Описание

производитель

AT91SAM9263
(Rev.:2009)

AT91 ARM Thumb Microcontrollers

Atmel Corporation 

the pins is only 1.8V without reprogramming the EBI0 voltage range. The user must be sure to

program the EBI0 voltage range before getting the device out of its Slow Clock Mode.

6. I/O Line Considerations

6.1 JTAG Port Pins

TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.

TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level

(VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can

be left unconnected for normal operations.

The NTRST signal is described in Section 6.3.

All JTAG signals except JTAGSEL (VDDBU) are supplied with VDDIOP0.

6.2 Test Pin

The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma-

nent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal

operations. Driving this line at a high level leads to unpredictable results.

This pin is supplied with VDDBU.

6.3 Reset Pins

NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven

with voltage at up to VDDIOP0.

NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the

processor.

As the product integrates power-on reset cells, which manage the processor and the JTAG

reset, the NRST and NTRST pins can be left unconnected.

The NRST and NTRST pins both integrate a permanent pull-up resistor of 100 kΩ minimum to

VDDIOP0.

The NRST signal is inserted in the Boundary Scan.

6.4 PIO Controllers

All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor of

100 kΩ typical. Programming of this pull-up resistor is performed independently for each I/O line

through the PIO Controllers.

After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which

are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral

at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing

tables on page 36 and following.

6.5 Shutdown Logic Pins

The SHDN pin is a tri-state output only pin, which is driven by the Shutdown Controller. There is

no internal pull-up. An external pull-up to VDDBU is needed and its value must be higher than 1

14 AT91SAM9263 Preliminary

6249HS–ATARM–27-Jul-09

Share Link: