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ADUM1246ARZ-RL7(RevA) Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге
Компоненты Описание
производитель
ADUM1246ARZ-RL7
(Rev.:RevA)
ADI
Analog Devices ADI
ADUM1246ARZ-RL7 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADuM1240/ADuM1241/ADuM1245/ADuM1246
Data Sheet
ELECTRICAL CHARACTERISTICS—VDD1 = 3.3 V, VDD2 = 2.5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 3.3 V, and VDD2 = 2.5 V. Minimum and maximum specifications apply over the entire
recommended operation range of 3.0 V ≤ VDD1 ≤ 3.6 V, 2.25 V ≤ VDD2 ≤ 2.75 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
For dc specifications and ac specifications, see Table 3 for parameters related to Side 1 operation, and see Table 6 for parameters related to
Side 2 operation.
Table 7.
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Side 1 to Side 2
Side 2 to Side 1
Change vs. Temperature
Pulse Width Distortion
Pulse Width
Propagation Delay Skew1
Channel Matching
Codirectional
Opposing Direction
Symbol
tPHL, tPLH
tPHL, tPLH
PWD
PW
tPSK
tPSKCD
tPSKOD
Min Typ Max
2
84
180
120 180
280
12
500
10
10
60
Unit
Mbps
ns
ns
ps/°C
ns
ns
ns
ns
ns
Test Conditions/Comments
Within PWD limit
50% input to 50% output
50% input to 50% output
|tPLH − tPHL|
Within PWD limit
1 tPSK is the magnitude of the worst case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
Table 8.
Parameter
SUPPLY CURRENT
ADuM1240/ADuM1245
ADuM1241/ADuM1246
Symbol Min Typ Max
IDD1
366
500
IDD2
168
375
IDD1
306
400
IDD2
240
375
Unit
µA
µA
µA
µA
Test Conditions/Comments
2 Mbps, no load
ELECTRICAL CHARACTERISTICS—VDD1 = 2.5 V, VDD2 = 3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 2.5 V, and VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range of 2.25 V ≤ VDD1 ≤ 2.75 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
For dc specifications and ac specifications, see Table 6 for parameters related to Side 1 operation, and see Table 3 for parameters related to
Side 2 operation.
Table 9.
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Side 1 to Side 2
Side 2 to Side 1
Change vs. Temperature
Pulse Width Distortion
Pulse Width
Propagation Delay Skew1
Channel Matching
Codirectional
Opposing Direction
Symbol
tPHL, tPLH
tPHL, tPLH
PWD
PW
tPSK
tPSKCD
tPSKOD
Min Typ Max
2
120 180
84
180
200
12
500
10
10
60
Unit
Mbps
ns
ns
ps/°C
ns
ns
ns
ns
ns
Test Conditions/Comments
Within PWD limit
50% input to 50% output
50% input to 50% output
|tPLH − tPHL|
Within PWD limit
1 tPSK is the magnitude of the worst case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
Rev. A | Page 6 of 24

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