AD5694BRUZ Просмотр технического описания (PDF) - Analog Devices
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AD5694BRUZ Datasheet PDF : 24 Pages
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AD5696/AD5694
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5696/AD5694
Data Sheet
VOUTA 1
GND 2
VDD 3
VOUTC 4
12 A1
11 SCL
10 A0
9 VLOGIC
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD MUST BE TIED TO GND.
Figure 3. Pin Configuration, 16-Lead LFCSP
VREF 1
VOUTB 2
VOUTA 3
GND 4
VDD 5
VOUTC 6
VOUTD 7
SDA 8
16 RSTSEL
15 RESET
AD5696/ 14 A1
AD5694
13 SCL
TOP VIEW
(Not to Scale) 12 A0
11 VLOGIC
10 GAIN
9 LDAC
Figure 4. Pin Configuration, 16-Lead TSSOP
Table 7. Pin Function Descriptions
Pin No.
LFCSP
TSSOP
Mnemonic
1
3
VOUTA
2
4
GND
3
5
VDD
4
6
VOUTC
5
7
VOUTD
6
8
SDA
7
9
LDAC
8
10
GAIN
9
11
VLOGIC
10
12
A0
11
13
SCL
12
14
A1
13
15
RESET
14
16
RSTSEL
15
1
VREF
16
2
VOUTB
17
N/A
EPAD
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Power Supply Input. The parts can be operated from 2.7 V to 5.5 V. The supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the
24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the
supply with an external pull-up resistor.
LDAC can be operated in two modes, asynchronous update mode and synchronous update mode.
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new
data; all DAC outputs are simultaneously updated. This pin can also be tied permanently low.
Gain Select Pin. When this pin is tied to GND, all four DAC outputs have a span of 0 V to VREF.
When this pin is tied to VLOGIC, all four DAC outputs have a span of 0 V to 2 × VREF.
Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.
Address Input. Sets the first LSB of the 7-bit slave address.
Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the
24-bit input shift register.
Address Input. Sets the second LSB of the 7-bit slave address.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is activated
(low), the input register and the DAC register are updated with zero scale or midscale, depending
on the state of the RSTSEL pin. When RESET is low, all LDAC pulses are ignored.
Power-On Reset Pin. When this pin is tied to GND, all four DACs are powered up to zero scale.
When this pin is tied to VLOGIC, all four DACs are powered up to midscale.
Reference Input Voltage.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
Rev. A | Page 8 of 24
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