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AT89C5131A-TISUL(2006) Просмотр технического описания (PDF) - Atmel Corporation

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AT89C5131A-TISUL
(Rev.:2006)
Atmel
Atmel Corporation Atmel
AT89C5131A-TISUL Datasheet PDF : 185 Pages
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AT89C5131A-L
Clock Controller
Introduction
The AT89C5131A-L clock controller is based on an on-chip oscillator feeding an on-chip
Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are gen-
erated by this controller.
The AT89C5131A-L X1 and X2 pins are the input and the output of a single-stage on-
chip inverter (see Figure 7) that can be configured with off-chip components as a Pierce
oscillator (see Figure 8). Value of capacitors and crystal characteristics are detailed in
the section “DC Characteristics”.
The X1 pin can also be used as input for an external 48 MHz clock.
The clock controller outputs three different clocks as shown in Figure 7:
• a clock for the CPU core
• a clock for the peripherals which is used to generate the Timers, PCA, WD, and Port
sampling clocks
• a clock for the USB controller
These clocks are enabled or disabled depending on the power reduction mode as
detailed in Section “Power Management”, page 152.
Figure 7. Oscillator Block Diagram
X1
X2
PLL
0
1
÷2
0
1
X2
C K CO N. 0
I DL
PCO N. 0
Peripheral
Clock
CPU Core
Clock
USB
Cl ock
EXT48
PL LC O N.2
PD
PCO N. 1
Oscillator
Two clock sources are available for CPU:
• Crystal oscillator on X1 and X2 pins: Up to 32 MHz
• External 48 MHz clock on X1 pin
In order to optimize the power consumption, the oscillator inverter is inactive when the
PLL output is not selected for the USB device.
13
4338E–USB–06/06

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