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74LVC821AD,118

10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

NXP Semiconductors. 

NXP Semiconductors

74LVC821A

10-bit D-type flip-flop; 5 V tolerance; positive-edge trigger; 3-state

tW

VI 90 %

negative

pulse

VM

10 %

0V

tf

VI

positive

pulse

tr

90 %

VM

10 %

0V

tW

VM

tr

tf

VM

VI

G

VCC

VO

DUT

VEXT

RL

RT

CL

RL

001aae331

Test data is given in Table 9.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 10. Load circuitry for switching times

Table 9. Test data

Supply voltage

1.2 V

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

3.0 V to 3.6 V

Input

VI

VCC

VCC

VCC

2.7 V

2.7 V

tr, tf

 2 ns

 2 ns

 2 ns

 2.5 ns

 2.5 ns

Load

CL

30 pF

30 pF

30 pF

50 pF

50 pF

RL

1 k

1 k

500 

500 

500 

VEXT

tPLH, tPHL

open

open

open

open

open

tPLZ, tPZL

2  VCC

2  VCC

2  VCC

2  VCC

2  VCC

tPHZ, tPZH

GND

GND

GND

GND

GND

74LVC821A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 23 November 2012

© NXP B.V. 2012. All rights reserved.

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