L9347 Просмотр технического описания (PDF) - STMicroelectronics
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L9347 Datasheet PDF : 21 Pages
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L9347
set on error and all power outputs are shut off. The status signals remain in their state until the clock signal is
present again. A clock failure during power on of VCC is detected only on the regulated channels. The status
outputs of the channel 1 and 2 are low in this case.
1.7 Drift Detection (regulated channels only)
The drift detection is used to compare the two regulated channels during regulation. This “Drift” test compares
the output PWM of the regulators. The resistivity of the load influences the output PWM. The approximated for-
mula for the output current below shows the dependency of the load resistor to the output PWM. In this formula
the energy reduction during the recirculation is not taken into account. The real output PWM is higher. The test-
mode is enabled with IN,EN and TEST high. With an identical 2kHz PWM-Signal connected to the IN-inputs the
output PWM must be in a range of +-14.3%. If the difference between the two on-times is more than ±14.3% of
the expected value an error is detected and monitored by the status outputs, in the same way as described
above, but a drift error will not be registered and also not delayed with TD as other errors
IOUT = R-----L-V----+-B----RA-----TO-----N--- ⋅ PWM
Drift Definition:
Drift = PWM(1+E) - PWM (1-E) = 2PWM E
Drift * 4 < PWM (1+E)
with E >14.3% a drift is detected
E.. not correlated Error of the channels
%PWM ... Corresponding ideal output PWM to a given input PWM
A 7bit output-PWM-register is used for the comparison. The register with the lower value is subtracted from the
higher one. This result is multiplied by four and compared with the higher value.
1.8 Other Test modes
The test pin is also used to test the regulated channels in the production. With a special sequence on this pin
the power stages of the regulated channels can be controlled direct from the input. No status feedback of the
regulated channels is given. The status output is clocked by the regulator logic. The output sequence is a indi-
cation of a proper logic functionality. The following table shows the functionality of this special test mode
EN
IN
TEST
OUT
STATUS
Note
1
X
X
X
X
disable test mode
1
1
1
on
1
Drift mode
0
X
off
test pattern
test condition one
0
X
off
test pattern
test condition two
0
X
off
test pattern
test condition three
0
0
off
test pattern
test condition four
0
1
on
test pattern
test condition four
For more details about the test condition four see timing diagram.
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