MF0ICU1001W(2010) Просмотр технического описания (PDF) - NXP Semiconductors.
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MF0ICU1001W Datasheet PDF : 28 Pages
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NXP Semiconductors
MF0ICU1
MIFARE Ultralight contactless single-ticket IC
8.5 Memory organization
The 512-bit EEPROM memory is organized in 16 pages with 4 bytes per page. In the
erased state the EEPROM cells are read as logic 0, in the written state as logic 1.
Table 4. Memory organization
Page address
Byte number
Decimal
Hex
0
0
00h
1
01h
2
02h
serial number
3
03h
OTP
4 to 15
04h to 0Fh
1
2
serial number
serial number
internal
lock bytes
OTP
OTP
user memory
3
lock bytes
OTP
8.5.1 UID/serial number
The unique 7-byte serial number (UID) and its two check bytes are programmed into the
first 9 bytes of memory covering page addresses 00h, 01h and the first byte of page 02h.
The second byte of page address 02h is reserved for internal data. These bytes are
programmed by the IC manufacturer and because of the security requirements are write
protected.
MSB
LSB
0 0 0 0 0 1 0 0 manufacturer ID for NXP Semiconductors (04h)
page 0
byte 0 1 2 3
serial number
part 1
check byte 0
page 1
0123
serial number
part 2
page 2
0123
check byte 1
internal
lock bytes
001aai001
Fig 6. UID/serial number
In accordance with ISO/IEC 14443-3 Check Byte0 (BCC0) is defined as CT ⊕ SN0 ⊕ SN1
⊕ SN2 and Check Byte 1 (BCC1) is defined as SN3 ⊕ SN4 ⊕ SN5 ⊕ SN6.
SN0 holds the Manufacturer ID for NXP Semiconductors (04h) in accordance with
ISO/IEC 14443-3 and ISO/IEC 7816-6 AMD.1
MF0ICU1
Product data sheet
PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.8 — 22 December 2010
028638
© NXP B.V. 2010. All rights reserved.
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