EVL6563H-100W Просмотр технического описания (PDF) - STMicroelectronics

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EVL6563H-100W

250 W transition-mode PFC pre-regulator with the new L6563H

STMicroelectronics 

AN3118

Test results and significant waveforms

Figure 15. EVL6563H-250W TM PFC: static Vout regulation vs. output power



















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The measured output voltage at different line and load conditions is reported in Figure 15.

As shown, the voltage is very stable over all the input voltage and output load range.

4.2

MOSFET current, TM signals, and L6563H THD optimizer

In the following images the waveforms relevant to the switch current at 100 Vac voltage

mains are reported; in Figure 16 and 17 it can be noted that the current peaks in the two

MOSFETs in parallel are very close to each other, demonstrating perfect current sharing

between the two devices. The two MOSFETs in parallel allow the total thermal resistance

junction-heat sink to decrease, therefore the same peak current can be managed using two

smaller and cheaper MOSFETs instead of one bigger one.

In Figure 16, close to the zero crossing points of the sinewave, it is possible to note the

action of the THD optimizer embedded in the L6563H. It is a circuit which minimizes the

conduction dead-angle occurring to the AC input current near the zero-crossings of the line

voltage (crossover distortion). In this way, the THD of the current is considerably reduced. A

major cause of this distortion is the inability of the system to transfer energy effectively when

the instantaneous line voltage is very low. This effect is magnified by the high frequency filter

capacitor placed after the bridge rectifier, which retains some residual voltage that causes

the diodes of the bridge rectifier to be reverse-biased and the input current flow to

temporarily stop. To overcome this issue the device forces the PFC pre-regulator to process

more energy near the line voltage zero-crossings as compared to that commanded by the

control loop. This results in both minimizing the time interval where energy transfer is

lacking, and fully discharging the high-frequency filter capacitor after the bridge. Essentially,

the circuit artificially increases the ON-time of the power switch with a positive offset added

to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is

reduced as the instantaneous line voltage increases, so that it becomes negligible as the

line voltage moves toward the top of the sinusoid. Furthermore, the offset is modulated by

the voltage on the VFF pin so as to have little offset at low line, where energy transfer at zero

crossings is typically quite good, and a larger offset at high line where the energy transfer

worsens.

Doc ID 16847 Rev 2

13/31

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