MU9C8148-FC Просмотр технического описания (PDF) - Unspecified

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MU9C8148-FC

SRT Interface

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MU9C8148

FUNCTIONAL DESCRIPTION (CONT’D)

Instruction Buffer

The Instruction buffer (IB) shown in Figure 1 consists of the

following: the 128-entry Instruction storage, the Instruction

pointer (IP), the Address pointer, the Start address registers,

the FIFO, and FIFO control registers.

The Instruction Storage (IS) can store up to seven down-loaded

routines which contain instructions for the LANCAM to execute,

plus room for data storage. The IS location accessed by the

Host processor port is controlled by an auto-incrementing

Address pointer, which is part of the Control register. Each

instruction is a 16-bit LANCAM op-code or data word along with

3 bits that indicate the level of /W, /CM, /EC during the

instruction. An additional S-bit is used to indicate whether this

entry is a LANCAM instruction or a MU9C8148 instruction.

The Instruction pointer (IP) points to the instruction currently

executing. At the start of a routine the IP is loaded with the

appropriate Start address. The IP can also be loaded from

Branch Routine addresses or addresses contained in an

instruction itself. For example, when a “Wait for a match”

instruction is executed and no match has occurred, the IP is

loaded with the address of the next instruction to execute.

The Start Address registers contain the start addresses of all

seven routines. When a routine is started, this address is

copied into the IP and execution is started. In addition to the

regular start addresses, two Branch Routine addresses are

available in the IB Start I register and are selected based on

the received frame type, as enabled in the Transparent

Bridging register. If a “Wait for match then execute at Branch

Routine address selected” instruction is executed and no match

occurs, the IP is loaded with the Branch Routine address

selected by the current frame type and execution continues.

Part of the IS may be used as a FIFO for data storage. Data

from the routines can be moved either to or from the Host

Processor interface through the FIFO. While routines are

loaded into the IS from 00H up towards 7FH, the FIFO goes

from 7FH down to the limit set in the FIFO control register. The

functionallity of the /FULL or /EMPTY flag is programmed in the

FIFO Control register to prevent FIFO overflow or underflow

situations.

Programming and Execution of Routines

either started directly, or after an RII has been received, or after

the second C bit of the Frame Status field has been received. If

the STDIR bit of a specific routine is set HIGH, the routine is

started immediately. If the START bit of a specific routine is set

to HIGH, the routine is started directly after an RII has been

received (SA/DA is HIGH) or after the second C bit has been

received (SA/DA is LOW). After execution has finished, the

START and STDIR bits are set LOW. If the AUTOSTART bit for

Routines 3, 4, 5 or 6 is set HIGH in the IB Start II register, that

routine is started for every frame received directly after an RII

has been received (when SA/DA is HIGH), or after the second

C bit has been received (when SA/DA is LOW). If more than

one routine should be started at the same time, the routine with

the numerically lowest start address is started first.

The TB block starts Routine 0, 1 or 2 when the enable bit of

that routine is set HIGH. Routines 0 and 2, used for DA

comparison, are started directly after the RII while Routine 1,

used for SA comparison, is started after the last C bit of the FS

field has been received, and if the frame was error-free.

Arbiter

The Arbiter block has two primary tasks: 1) Arbitration between

the execution of different routines stored in the Instruction

Buffer; and, 2) Arbitration between two MU9C8148's when they

are sharing the same LANCAM.

Routine Priorities

Of the seven routines stored in the Instruction buffer, execution

of Routines 0–2 is time critical because there is a direct relation

to the incoming data stream of the Token Ring; therefore, they

have the highest priority and cannot be interrupted by other

routines. The time length of Routines 0 or 2 plus Routine 1

must fit in the time interval of a minimum length frame.

Routines 3–6 have a lower priority and they can be interrupted

by routines having a lower number.

During execution of Routine 0–2, no lower priority routine can

be started. When a second routine is programmed to be started

and execution of the first routine has ended, this second routine

is started immediately afterward. A currently running routine

can be interrupted by a higher priority routine, and the lower

priority routine will re-start from the beginning immediately after

the interrupting routine is finished.

The IS is loaded and read through the IB register in two 16-bit

cycles. The first 16-bit cycle moves the data on the D15–D0

lines of the Host Processor interface into the data field of the

location in the IB indicated by the Address pointer in the

Control register, or vice-versa in case of a read from the IB

register. The second 16-bit word is written to or read from the

/W, /CM, /EC, and /S bits of that same location.

The Control register contains an Address pointer that selects

the accessed location in the IS. The Address pointer can be

read out or overwritten. It is incremented when the Host

processor has completed the two write or read cycles to one

location of the IB.

Routines in the instruction buffer can be started either by the

Host processor (Routines 3–6 only) or the Transparent Bridging

block. If a routine is started by the Host processor, it can be

Host Processor Access

The Address bus, A(4-0), is used to select the Registers,

Instruction Buffer, or LANCAM for access from the Host

processor port. Direct access to the LANCAM through registers

18H to 1FH should only be used for LANCAM initialization and

should be completed prior to enabling IB routines. After that,

new addresses written to the LANCAM by the host processor

should be first stored in the IB, and a routine started that

transfers it to the LANCAM. Access to the IB is arbitrated if

network activity triggers a pre-stored routine. The /INT pin goes

LOW (the INT bit in the Control register goes HIGH) to notify

the host processor that a routine is running. (If an access to the

IB is attempted while /INT is LOW, the return of /HBRDY is

delayed slightly until the routine instruction currently executing

is completed.) /INT will stay LOW until all routines have

completed. The processor can then re-issue its request.

Rev. 5.5 Draft web

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