83C196MD Просмотр технического описания (PDF) - Intel
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83C196MD Datasheet PDF : 25 Pages
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8XC196MD
87C196MD DESIGN
CONSIDERATIONS
When an indirect shift during divide occurs the upper
3 bits of the shift count are not masked completely
If the shift count register has the value 32 n where
n e 1 3 5 or 7 the operand will be shifted 32 times
This should have resulted in no shift taking place
8XC196MC to 8XC196MD Design
Considerations
8XC196MC and 8XC196MD are pin compatible
However there were several pins that were not con-
nected (NC) on the 8XC196MC that are I O pins on
the 8XC196MD Port 7 is a bidirectional port added
to the 8XC196MD Port 1 has one additional analog
or digital input that was connected to VSS on the
8XC196MC Port 1 also has two additional digital in-
puts See 8XC196MC and 8XC196MD Differences
Section of this data sheet
DATA SHEET REVISION HISTORY
This is the initial data sheet (272323-001) It is valid
for devices with a ‘‘B’’ at the end of the topside
tracking number Data sheets are changed as new
device information becomes available Verify with
your local Intel sales office that you have the latest
version before finalizing a design or ordering devic-
es
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