UPD70433GJ-16-3EB Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD70433GJ-16-3EB Datasheet PDF : 166 Pages
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µPD70433
3. CPU FUNCTIONS
The CPU of the V55PI is software upword compatible with the V20 and V30 (native mode), and the V25 and V35.
3.1 FEATURES
• Software upward compatible with V20 & V30 (native mode) and V25 & V35 (includes additional instructions)
• Minimum instruction cycle: 160 ns/12.5 MHz (external 25 MHz clock)
125 ns/16 MHz (external 32 MHz clock)
• Address space: 16M bytes
1M-byte basic memory (program) space
16M-byte extended memory (data) space
• Register file space (in on-chip RAM): 512 bytes/16 register banks
• I/O space: 64K bytes
• Register configuration (compared with V20/V30 and V25/V35)
Item
Extended segment register
Register bank
Mode flag
PSW
Register bank flags
Input/output instruction
trap flag
User flag
Special function register area
V20, V30
None
None
MD
None
None
None
None
V25, V35
None
8 banks (in memory space)
None
RB0 to RB2
V55PI
DS2, DS3
16 banks (in register file space)
None
RB0 to RB3
IBRK
F0, F1
240 bytes
(memory mapping onto
FFF00H to FFFEFH)
IBRK
None
496 bytes
(memory mapping onto
FFE00H to FFFEFH)
• Internal 16-bit architecture, switchable external data bus width (16/8 bits)
• Automatic wait control with memory divided in variable sizes (max. 6 blocks)
• Programmable wait function
• Wait function using READY pin
• Refresh function
• Automatic generation of refresh cycle (RAS only)
• RAS pin functions
RAS pin
→ DRAM RAS timing
RD, WRH, WRL pins → DRAM CAS timing
ASTB pin
→ DRAM row/column address switching timing
16
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