82C55A_15 Просмотр технического описания (PDF) - Intersil

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производитель

82C55A_15

CMOS Programmable Peripheral Interface

Intersil 

82C55A

CONTROL WORD

D7 D6 D5 D4 D3 D2 D1 D0

11

1/0 1/0 1/0

PC2-PC0

1 = INPUT

0 = OUTPUT

PORT B

1 = INPUT

0 = OUTPUT

GROUP B MODE

0 = MODE 0

1 = MODE 1

FIGURE 11. MODE CONTROL WORD

PC3

INTRA

PA7-PA0 8

PC7

INTE

1

PC6

OBFA

ACKA

INTE

2

PC4

STBA

PC5

IBFA

WR

RD

PC2-PC0

3

I/O

FIGURE 12. MODE 2

DATA FROM

CPU TO 82C55A

WR

OBF

INTR

ACK

STB

tWOB

tST

tAOB

tAK

IBF

PERIPHERAL

BUS

tSIB

tPS

tPH

tAD

tKD

tRIB

RD

DATA FROM

DATA FROM

PERIPHERAL TO 82C55A

82C55A TO PERIPHERAL

DATA FROM

82C55A TO CPU

NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF  MASK  STB  RD + OBF  MASK

 ACK  WR)

FIGURE 13. MODE 2 (BIDIRECTIONAL)

FN2969 Rev 11.00

Dec 8, 2015

Page 12 of 30

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