CXD2085M Просмотр технического описания (PDF) - Sony Semiconductor

Номер в каталоге

Компоненты Описание

производитель

CXD2085M

ID-1 Detection

Sony Semiconductor 

CXD2085M

4. Clock

The CXD2085M requires a 4fsc clock (14.318MHz). When using a crystal oscillator, connect it between XI (Pin

13) and XO (Pin 12).

When inputting the clock from an external source, input it to XI (Pin 13).

5. Various Settings and Data I/O

The various settings and data I/O can be made by using the pin directly or using I2C bus interface.

5-1. I2C bus

By setting MCON (Pin 3) to High, the various settings and data extraction can be made with the I2C bus.

The CXD2085M supports the I2C bus slave RECEIVER and slave TRANSMITTER modes. The slave address

is 40 (H).

In addition to standard mode (max. 100K bits/s), this IC also supports high-speed mode (max. 400K bits/s).

Even when the power supply falls to 0V, it does not occupy the I2C bus. However, the absolute maximum

ratings should not be exceeded.

The I2C bus transmission process is shown in the figure below.

The number of transmission data is one byte for write (RECEIVER) and two bytes for read (TRANSMITTER).

There is no sub-address setting function. Note that the I2C bus transmission cannot be performed during

resetting by the XRST pin (Pin 1).

Data write (RECEIVER mode)

7654321 0 1 76543210 1

Sm SLAm Wm As DATAm As P

Data read (TRANSMITTER mode)

7654321 0 1 76543210 1 76543210 1

Sm SLAm Rm As DATAs Am DATAs XAm P

Symbol

∗m

∗s

S

P

SLA

DATA

W

R

A

XA

Description

from Master to Slave

from Slave to Master

Start Condition

Stop Condition

Slave Address

Data

0: Write Master → Slave

1: Read Slave → Master

Clock pulse for Acknowledgment (SDA: L)

Acknowledgment none (SDA: H)

–6–

Share Link: