HA5340
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as applica-
tion and design information only. No guarantee is implied.
Performance Curves VS = ±15V, TA = +25oC, Unless Otherwise Specified.
TACQ POS 0 TO +10 STEP
TACQ vs. ADDITIONAL CH
S/H
CONTROL
S/H
CONTROL
VOUT
DROOP RATE vs. HOLD CAPACITOR SIZE
VOUT
ACQUISITION TIME (0.01%) vs. HOLD CAPACITANCE
HOLD STEP ERROR vs. TRISE
CH = Internal; Temperature +25oC
HOLD STEP ERROR vs. HOLD CAPACITANCE
TRISE = 5ns; Temperature = +25oC
Spec Number 511117-883
7-17