IDT70V05L(1996) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT70V05L
(Rev.:1996)

HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT70V05S/L

HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)

IDT70V05X25

IDT70V05X35

Symbol

Parameter

BUSY TIMING (M/S = VIH)

tBAA

BUSY Access Time from Address Match

tBDA

BUSY Disable Time from Address Not Matched

tBAC

BUSY Access Time from Chip Enable Low

tBDC

BUSY Disable Time from Chip Enable High

tAPS

Arbitration Priority Set-up Time(2)

tBDD

BUSY Disable to Valid Data(3)

tWH

Write Hold After BUSY(5)

Min. Max. Min.

Max.

—

25

—

35

—

25

—

35

—

25

—

35

—

25

—

35

5

—

5

—

—

35

—

40

20

—

25

—

IDT70V05X55

Min. Max. Unit

—

45

ns

—

45

ns

—

45

ns

—

45

ns

5

—

ns

—

50

ns

25

—

ns

BUSY TIMING (M/S = VIL)

tWB

BUSY Input to Write(4)

tWH

Write Hold After BUSY(5)

0

—

0

—

0

—

ns

20

—

25

—

25

—

ns

PORT-TO-PORT DELAY TIMING

tWDD

Write Pulse to Data Delay(1)

tDDD

Write Data Valid to Read Data Delay(1)

—

55

—

65

—

85

ns

—

50

—

60

—

80

ns

NOTES:

2941 tbl 13

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH) or "Timing Waveform

of Write With Port-To-Port Delay (M/S=VIL)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited during contention.

5. To ensure that a write cycle is completed after contention.

6. "X" is part numbers indicates power rating (S or L).

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ WITH BUSY (M/S = VIH)(2,4,5)

tWC

ADDR"A"

W R/ "A"

MATCH

tWP

tDW

tDH

DATAIN "A"

tAPS (1)

VALID

ADDR"B"

BUSY"B"

MATCH

tBDA

tBDD

tWDD

DATAOUT "B"

tDDD (3)

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).

2. CEL = CER = VIL.

3. OE = VIL for the reading port.

4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.

5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".

VALID

2941 drw 13

6.35

10

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