LF3370 Просмотр технического описания (PDF) - LOGIC Devices

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LF3370

High-Definition Video Format Converter

LOGIC Devices 

DEVICES INCORPORATED

LF3370

High-Definition Video Format Converter

SIGNAL DEFINITIONS

HF1/HF0 — HBlank Flags

HBLANK — Horizontal Blanking Control

Power

VCC and GND

+3.3 V power supply. All power pins

must be connected.

HF1 and HF0 are two general purpose

flags used to indicate when a 20-bit

counter reaches its user-defined

terminal count; a HIGH to LOW

transition of HBLANK and/or RESET

will reset the flags.

HBLANK is used for data replacement

corresponding to user-selectable

blanking levels. A HIGH to LOW

transition resets the counter and the

HFx flags.This signal is latched on the

rising edge of CLK.

Clock

CLK — Master Clock

The rising edge of CLK strobes all

enabled registers. To guarantee data

integrity, a minimum of 25KHz must

be maintained.

Inputs

A12-0, B12-0, C12-0, D12-0 — Data Inputs

A12-0, B12-0, C12-0, and D12-0 are the

13-bit registered data input ports.

Data is latched on the rising edge of

CLK.

CF12-0 — Coefficient Input

CF12-0 is used to address and load

Colorspace/Key Scaler coefficient

banks, Round/Select/Limit registers,

and Configuration registers. Data

present on CF12-0 is latched into the

LF InterfaceTM on the rising edge of

CLK when LD is LOW.

CA1-0 — Coefficient Address

CA1-0 determines which of the four

user-programmable Colorspace/Key

Scaler Coefficients are used.

Outputs

W12-0 , X12-0 , Y12-0 , Z12-0 — Data Outputs

Controls

LD — Configuration Load

When LD is LOW, data on CF12-0 is

latched into the LF3370 LF InterfaceTM

on the rising edge of CLK. When LD

is HIGH, data is not loaded into

the LF InterfaceTM. When enabling

the LF InterfaceTM for data input, a

latched HIGH to LOW transition of

LD is required in order for the input

circuitry to function properly.

Therefore, LD must be set HIGH

immediately after power up to

ensure proper operation of the input

circuitry.

SYNC — Synchronization for data alignment

SYNC control signal is required to

properly synchronize the input

demultiplexer, output multiplexer,

and halfband filters to the data

flowing through the LF3370. A

latched HIGH to LOW transition tells

the core which sample corresponds to

a Cb/Cr sample for proper de-multi-

plexing and multiplexing. This signal

will also synchronize the half-band

filters into a decimation/interpolation

sequence. This signal is latched on the

rising edge of CLK.

DATAPASS — Datapass Mode

INBIAS1-0 — Input Bias Control

INBIAS1-0 determines which of the

four user-programmable Input Bias

registers are used to sum with the

input data. These pins are latched on

the rising edge of CLK.

OUTBIAS1-0 — Output Bias Control

OUTBIAS1-0 determines which of the

four user-programmable Output Bias

registers are used to sum with the

output data.These pins are latched on

the rising edge of CLK.

RSL1-0 — Round/Select/Limit Control

RSL1-0 determines which of the user-

programmable Round/Select/Limit

registers (RSL registers) are used in

the RSL circuitry. A value of 00 on

RSL1-0 selects RSL register 0. A value

of 01 selects RSL register 1 and so on.

RSL1-0 is latched on the rising edge of

CLK.

OE — Output Enable

When OE is LOW, W12-0, X12-0, Y12-0,

and Z12-0 are enabled for output.

When OE is HIGH, W12-0, X12-0, Y12-0,

and Z12-0 are placed in a high-

impedance state.

W12-0, X12-0, Y12-0, and Z12-0 are the

13-bit registered data output ports.

Outputs are updated on the rising

edge of CLK.

DATAPASS is used to place the

LF3370 in a mode of operation that

allows the user to pass data through

the core (Input/Output Bias Adders,

LUTs, Hafband Interpolator/

Decimator, Colorspace/Key Scaler)

without any processing. This signal is

latched on the rising edge of CLK.

PAUSE — LF InterfaceTM Pause

When PAUSE is HIGH, the LF3370

LF InterfaceTM loading sequence is

halted until PAUSE is returned to a

LOW state. This effectively allows

the user to load coefficients and

control registers at a slower rate than

the master clock. This pin is latched

Video Imaging Products

4

03/13/2001–LDS.3370-F

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