MU9C2485L-90TCC Просмотр технического описания (PDF) - MUSIC Semiconductors

Номер в каталоге

Компоненты Описание

производитель

MU9C2485L-90TCC

WidePort LANCAM® Family

MUSIC Semiconductors 

WidePort LANCAM® Family

INSTRUCTION SET DESCRIPTIONS§

Instruction: Select Persistent Source (SPS)

Binary Op-Code: 0000 f000 0000 0sss*

f

Address Field flag†

sss

Selected source

This instruction selects a persistent source for data reads,

until another SPS instruction changes it or a reset occurs.

The default source after reset for Data Read cycles is the

Comparand register. Setting the persistent source to

M@aaaH loads the Address register with “aaaH,” and the

first access to that persistent source will be at aaaH, after

which the AR value increments or decrements as set in the

Control register. The SPS M@[AR] instruction does the

same except the current Address Register value is used.

Instruction: Select Persistent Destination (SPD)

Binary Op-Code: 0000 f001 mmdd dvvv*

f

Address Field flag†

mm

Mask Register select

ddd

Selected destination

vvv

Validity setting for Memory Location

destinations

This instruction selects a persistent destination for data

writes, which remains until another SPD instruction changes

it or a reset occurs. The default destination for Data Write

cycles is the Comparand register after a reset. When the

destination is the Comparand register or the memory array,

the data written may be masked by either Mask Register 1

or Mask Register 2, so that only destination bits

corresponding to bits in the mask register set to 0 will be

modified. An automatic compare will occur after writing the

last segment of the Comparand or mask registers, but not

after writing to memory. Setting the persistent destination

to M@aaaH loads the Address register with “aaaH,” and

the first access to that persistent destination will be at aaaH,

after which the AR value increments or decrements as set

in the Control register. The SPD M@[AR] instruction does

the same except the current Address Register value is used.

Instruction: Temporary Command Override

(TCO)

Binary Op-Code: 0000 f010 00dd d000*

f

Address Field flag†

ddd

Register selected as source or

destination for only the next

Command Read or Write cycle

The TCO instruction temporarily redirects the DQ bus for

register access. If f=1, a register write will be performed

with the data on DQ15–0. If f=0, a subsequent Command

Read cycle reads the register contents through DQ15–0.

During register reads, DQ31–16 will contain the upper 16-

bits of the Status register, except in the case of a Page

Address register read where these bits are 0s. After the

access, subsequent Command Read or Write cycles revert

to reading the Status register and writing to the Instruction

decoder. All registers except the Status, NF, PS, and PD are

available for write access. All registers are available for

read access. The complete Status register is only available

through a non-TCO Command Read access. Reading the

PS register also outputs the Device ID on bits 15–4, as

shown in Table 13.

Instruction: Data Move (MOV)

Binary Op-Code: 0000 f011 mmdd dsss or

0000 f011 mmdd dvss*

f

Address Field flag†

mm

Mask Register select

ddd

Destination of data

sss

Source of data

v

Validity setting if destination is a

Memory location

The MOV instruction performs a 64-bit move of the data in

the selected source to the selected destination. If the source

or destination is aaaH, the Address register is set to “aaaH.”

For MOV instructions to or from aaaH or [AR], the Address

register will increment or decrement from that value after

the move completes, as set in the Control register. Data

transfers between the Memory array and the Comparand

register may be masked by either Mask Register 1 or Mask

Register 2, in which case, only those bits in the destination

which correspond to bits in the selected mask register set

to 0 will be changed. A Memory location used as a

destination for a MOV instruction may be set to Valid or

left unchanged. If the source and destination are the same

register, no net change occurs (a NOP).

Instruction: Validity Bit Control (VBC)

Binary Op-Code: 0000 f100 00dd dvvv*

f

Address Field flag†

ddd

Destination of data

vvv

Validity setting for Memory location

The VBC instruction sets the Validity bits at the selected

memory locations to the selected state. This feature can be

used to find all valid entries by using a repetitive sequence

of CMP V through a mask of all 1s followed by a VBC HM,

S. If the VBC target is aaaH, the Address register is set to

“aaaH.” For VBC instructions to or from aaaH or [AR], the

Address register will increment or decrement from that value

after the operation completes, as set in the Control register.

17

Rev. 2

Share Link: