MC12439FN Просмотр технического описания (PDF) - Motorola => Freescale
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MC12439FN Datasheet PDF : 11 Pages
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MC12439
VCC FOUT FOUT GND VCC TEST GND
25 24 23 22 21 20 19
S_CLOCK 26
18 N[1]
S_DATA 27
S_LOAD 28
PLL–VCC 1
17 N[0]
16 NC
15 XTAL_SEL
N[1:0]
00
01
10
11
Output Division
2
4
8
1
PWR_DOWN 2
FREF_EXT 3
XTAL1 4
56
14 M[6]
13 M[5]
12 M[4]
7 8 9 10 11
Input
0
PWR_DOWN FOUT
XTAL_SEL FREF_EXT
OE
Disabled
1
FOUT/16
XTAL
Enabled
XTAL2 OE P_LOAD M[0] M[1] M[2] M[3]
PIN DESCRIPTIONS
Pin Name
Type
Inputs
XTAL1, XTAL2
—
S_LOAD
Int. Pulldown
S_DATA
S_CLOCK
P_LOAD
Int. Pulldown
Int. Pulldown
Int. Pullup
M[6:0]
N[1:0]
OE
Outputs
FOUT, FOUT
TEST
Power
VCC
PLL_VCC
GND
Other
PWR_DOWN
FREF_EXT
XTAL_SEL
Int. Pullup
Int. Pullup
Int. Pullup
—
—
—
—
—
Int. Pulldown
Int. Pulldown
Int. Pullup
Figure 1. 28–Lead Pinout (Top View)
Function
These pins form an oscillator when connected to an external series–resonant crystal.
This pin loads the configuration latches with the contents of the shift registers. The latches will be
transparent when this signal is HIGH, thus the data must be stable on the HIGH–to–LOW transition of
S_LOAD for proper operation.
This pin acts as the data input to the serial configuration shift registers.
This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising
edge.
This pin loads the configuration latches with the contents of the parallel inputs .The latches will be
transparent when this signal is LOW, thus the parallel data must be stable on the LOW–to–HIGH transition
of P_LOAD for proper operation.
These pins are used to configure the PLL loop divider. They are sampled on the LOW–to–HIGH transition
of P_LOAD. M[6] is the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled on the LOW–to–HIGH
transition of P_LOAD.
Active HIGH Output Enable.
These differential positive–referenced ECL signals (PECL) are the output of the synthesizer.
The function of this output is determined by the serial configuration bits T[2:0].
This is the positive supply for the chip, and is connected to +3.3V or 5.0V (VCC = PLL_VCC).
This is the positive supply for the PLL, and should be as noise–free as possible for low–jitter operation. This
supply is connected to +3.3V or 5.0V (VCC = PLL_VCC).
These pins are the negative supply for the chip and are normally all connected to ground.
LVCMOS input that forces the FOUT output to synchronously reduce its frequency by a factor of 16.
LVCMOS input which can be used as the PLL reference frequency.
LVCMOS input that selects between the XTAL and FREF_EXT PLL reference inputs. A HIGH selects the
XTAL input.
MOTOROLA
2
TIMING SOLUTIONS
BR1333 — Rev 6
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