Z85C3016VEG Просмотр технического описания (PDF) - Zilog

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производитель

Z85C3016VEG

CMOS SCC Serial Communications Controller

Zilog 

CMOS SCC Serial Communications Controller

Product Specification

9

CE

Chip Enable (input, active Low) . This signal selects the SCC for a Read or Write opera-

tion

D7–D0

Data Bus (bidirectional, tri-state) . These lines carry data and command to and from the

SCC.

D/C

Data/Control Select (input) . This signal defines the type of information transferred to or

from the SCC. A High indicates a data transfer; a Low indicates a command.

RD

Read (input, active Low) . This signal indicates a Read operation and when the SCC is

selected, enables the SCC’s bus drivers. During the Interrupt Acknowledge cycle, this sig-

nal gates the interrupt vector onto the bus if the SCC is the highest priority device request-

ing an interrupt.

WR

Write (input, active Low) . When the SCC is selected, this signal indicates a Write oper-

ation. The coincidence of RD and WR is interpreted as a reset.

Z80C30

The following links refer to descriptions of the pin functions specific to the Z80C30

device.

• AD7–AD0

• AS

• CS0

• CS1

• DS

• R/W

PS011706-0511

Pin Descriptions

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