X24645FP Просмотр технического описания (PDF) - IC MICROSYSTEMS
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X24645FP Datasheet PDF : 18 Pages
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X24645
Bus Timing
SCL
SDA IN
t
SU:STA
t
F
t
HIGH
t
LOW
t
HD:STA
t
HD:DAT
t
SU:DAT
t
R
t
SU:STO
t
t
AA
DH
t
BUF
SDA OUT
Write Cycle Limits
Symbol
TW R (6)
Parameter
Write Cycle Time
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/program cycle. During the write cycle, the
Bus Timing
2783 ILL F17
Min.
Typ.(5)
Max.
Units
5
10
ms
2783 FRM T11
X24645 bus interface circuits are disabled, SDA is
allowed to remain HIGH, and the device does not
respond to its slave address.
SCL
SDA
8th BIT
ACK
WORD n
t
WR
STOP
CONDITION
START
CONDITION
2783 ILL F18
Notes: (5)Typical values are for TA = 25°C and nominal supply voltage (5V).
(6)tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
120
100
80
60
40
V
R
MIN
= CC MAX
I
OL MIN
t
R
MAX
=R
C
BUS
MAX.
RESISTANCE
=1.8KΟ
20 MIN.
RESISTANCE
0
0 20 40 60
80100120
BUS CAPACITANCE (pF)
2783 ILL F19
SYMBOL TABLE
WAVEFORM INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
13
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