UC3842ADR2G Просмотр технического описания (PDF) - ON Semiconductor
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производитель
UC3842ADR2G Datasheet PDF : 18 Pages
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UC3842A, UC3843A, UC2842A, UC2843A
Vref
8(14)
RT
R
Bias
R
External
Sync
0.01
CT
4(7)
Input
47
2(3)
1(1)
Osc
+
+
−
EA
2R
R
5(9)
The diode clamp is required if the Sync amplitude is large enough to
cause the bottom side of CT to go more than 300 mV below ground.
Figure 21. External Clock Synchronization
VCC
7(12)
RA
8
4
RB
6
5.0k
+−
R
5
Q
3
2
+
−
S
7
C
5.0k MC1455
1
f=
1.44
(RA + 2RB)C
RB
Dmax = RA + 2RB
8(14)
R
Bias
R
Osc
4(7)
+
+
−
2(3)
EA
2R
R
1(1)
To
5(9)
Additional
UCX84XA’s
Figure 22. External Duty Cycle Clamp and
Multi Unit Synchronization
Vin
8(14)
4(7)
R2
2(3)
1(1)
R1
R
Bias
R
Osc
+
+
−
EA
1.0mA
2R
R
5.0Vref
+ +−
−
+− +
−
VClamp
−+
1.0V
S
RQ
Comp/Latch
5(9)
7(11)
Q1
6(10)
5(8)
3(5)
RS
VClamp =
1.67
R2 + 1
R1
+ 0.33 x 10 − 3
R1 R2
R1 + R2
Ipk(max) =
VClamp
RS
Where: 0 ≤ VClamp ≤ 1.0 V
Figure 23. Adjustable Reduction of Clamp Level
8(14)
R
Bias
R
5.0Vref
+ +−
−
Osc
4(7)
+
2(3)
1.0M
C
1(1)
+
−
EA
1.0mA
2R
R
S
−+
RQ
1.0V
5(9)
tSoft−Start 3600C in mF
Figure 24. Soft−Start Circuit
VCC
7(12)
Vin
8(14)
R
5.0Vref
+− +
Bias
R
+ +−
−
7(11)
−
Q1
Osc
4(7)
2(3)
R2
1(1)
+
+−
EA
1.0mA
2R
R
VClamp
−+
S
Q
R
Comp/Latch
1.0V
6(10)
5(8)
3(5)
RS
C
MPSA63
R1
1.67
VClamp =
R2 + 1
R1
5(9)
Ipk(max) =
VClamp
RS
tSoftstart = − In
Where: 0 ≤ VClamp ≤ 1.0 V
1−
VC
3VClamp
C
R1 R2
R1 + R2
VCC
(12)
Vin
RS Ipk rDS(on)
VPin 5 = rDM(on) + RS
5.0Vref
+ +−
−
+− +
−
If: SENSEFET = MTP10N10M
RS = 200
Then: Vpin 5 = 0.075 Ipk
D SENSEFET
(11)
S
S
−
+
RQ
Comp/Latch
Control CIrcuitry
Ground:
To Pin (9)
(10) G M
(8)
(5) RS
1/4 W
K
Power Ground
To Input Source
Return
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over current conditions, a
reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 23 and 25.
Figure 25. Adjustable Buffered Reduction of
Clamp Level with Soft−Start
Figure 26. Current Sensing Power MOSFET
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