NXP Semiconductors
7. Pinning information
7.1 Pinning
TDA19978A
Quad HDMI 1.3a receiver with digital processing
1
108
36
TDA19978AHV
73
Fig 2. Pin configuration (HLQFP144)
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7.2 Pin description
Table 3. Pin description
Symbol
Pin
VSSC
1
PD
2
VDDH(3V3)
3
RXDC+
4
RXDC−
5
VSSH
6
RXCC−
7
RXCC+
8
VDDH(3V3)
9
RXD0+
10
RXD0−
11
VSSH
12
RXC0−
13
RXC0+
14
VDDH(1V8)
15
RXD1+
16
RXD1−
17
VSSH
18
RXC1−
19
RXC1+
20
VDDH(3V3)
21
RXD2+
22
RXD2−
23
Type[1] Description
G
ground for the digital core
I
power-down control input (active HIGH)
P
HDMI receiver supply voltage; 3.3 V
I
HDMI input D positive clock channel
I
HDMI input D negative clock channel
G
HDMI receiver ground
I
HDMI input C negative clock channel
I
HDMI input C positive clock channel
P
HDMI receiver supply voltage; 3.3 V
I
HDMI input D positive data channel 0
I
HDMI input D negative data channel 0
G
HDMI receiver ground
I
HDMI input C negative data channel 0
I
HDMI input C positive data channel 0
P
HDMI receiver supply voltage; 1.8 V
I
HDMI input D positive data channel 1
I
HDMI input D negative data channel 1
G
HDMI receiver ground
I
HDMI input C negative data channel 1
I
HDMI input C positive data channel 1
P
HDMI receiver supply voltage; 3.3 V
I
HDMI input D positive data channel 2
I
HDMI input D negative data channel 2
TDA19978A_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 16 April 2010
© NXP B.V. 2010. All rights reserved.
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