AD6459 Просмотр технического описания (PDF) - Analog Devices

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AD6459

GSM 3 V Receiver IF Subsystem

Analog Devices 

AD6459

AD6459 EVALUATION BOARD

The AD6459 evaluation board (Figure 27) consists of a

AD6459, ground plane, I/O connectors, and a 19.5 MHz band

pass filter. The RF, LO and FREF ports are terminated in 50 Ω

to provide a broadband match or external signal generators.

The board provides SMA connectors for the RF, LO, demodu-

lator reference, mixer output and IF input signals. The MXOP

and IFIP connectors are left unconnected and are provided as a

testing convenience. Footprints for broadband matching trans-

formers and matching components are also provided to aid in

stage breakout testing.

The remaining low frequency signals, including the I and Q

interface, bias and power connections are made via a dual row

pin header that acts as an Interface Connector located along the

edges of the board. An on-board gain-reference 1.2 V biasing

option is provided via a single jumper, J1. The evaluation board

will not function without this jumper unless an external bias

GREF is provided from an external reference that is normally

provided by the associated ADC.

Full Path Configuration

As received, the board is configured for full-path evaluation

from RFHI to the I and Q outputs. The one-pole LC resonant

circuit provided represents a simple, yet balanced, IF bandpass

filtering approach. The filter supplied is centered at 19.5 MHz,

a common GSM intermediate frequency. Table I highlights the

filter component values for other IF frequencies. RFHI and

RFLO are true differential inputs, however for testing conve-

nience, the RFLO terminal of the AD6459 is ac referenced to

ground on the evaluation board. The GAIN bias input, which is

bypassed with a 10 nF capacitor, is brought out to the interface

connector. The PRUP input is provided with a 20 kΩ pull up

resistor to VPOS that activates the board.

The four differential I and Q outputs are brought out uncondi-

tioned, directly to the interface connector. A high impedance,

high bandwidth FET-type probe should be used when measur-

ing the I and Q ports. Excessive capacitive or resistive loading of

these ports will severely limit the video bandwidth and signal

swing. The demodulator PLL filter installed on the evaluation

board (R8, C10) can accommodate the full VFQO lock range

specified.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

0.295 (7.50)

0.271 (6.90)

20

11

1

10

0.078 (1.98) PIN 1

0.068 (1.73)

0.07 (1.78)

0.066 (1.67)

0.008 (0.203)

0.002 (0.050)

0.0256

(0.65)

BSC

8°

SEATING 0.009 (0.229) 0°

PLANE 0.005 (0.127)

0.037 (0.94)

0.022 (0.559)

–12–

REV. 0

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