CXD2930BR Просмотр технического описания (PDF) - Sony Semiconductor

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CXD2930BR

GPS LSI with Built-in 32-bit RISC CPU

Sony Semiconductor 

CXD2930BR

External Data Access Timing (ICS0, ISC1)

(1) Read (half-word access)

CLKOUT

IADR

ICS0, ICS1

IRD

IB

(a)

(b)

(c)

(e)

(g)

(16)

(d)

(f)

(h)

(2) Write (half-word access)

CLKOUT

IADR

ICS0, ICS1

IWR

IB

(a)

(b)

(c)

(d)

(i)

(j)

(k)

(16)

(l)

No.

Item

(a) Read/write cycle time (Fex: @9.207MHz)

(b) Address delay time

(c) Chip select fall delay time

(d) Chip select rise delay time

(e) Read signal fall delay time

(f) Read signal rise delay time

(g) Read data setup time

(h) Read data hold time

(i) Write signal fall delay time

(j) Write signal rise delay time

(k) Write data established time

(l) Write data hold time

– 17 –

Min. Typ. Max. Unit

—

108

—

ns

—

—

5

ns

2

—

10

ns

2

—

9

ns

1

—

3

ns

1

—

5

ns

8

—

—

ns

0

—

—

ns

0

—

1

ns

0

—

2

ns

—

—

5

ns

5

—

—

ns

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