CXA1951AQ Просмотр технического описания (PDF) - Sony Semiconductor

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производитель

CXA1951AQ

GPS Down Converter

Sony Semiconductor 

CXA1951AQ

4. NSW (Pin 1)

The internal counter frequency division value is determined by connecting this pin to VCC or GND when

selecting fo or 4 fo for IF, as shown in the table below.

IF

NSW

VCO counter

Reference frequency counter

fo

VCC

338 frequency division

4 frequency division

4fo

GND

570 frequency division

6 frequency division

5. CPOUT (Pin 2)

A current output charge pump configures an external loop filter for VCO control voltage.

R2

2

R1

C2

C1

6. FC (Pin 37)

This pin performs two functions when connected to VCC or GND; CPOUT (Pin 2) output status switching

and TEST OUT (Pin 38) selector switch. (See Table 1)

7. TEST OUT (Pin 38)

This is the monitor pin for the internal counter frequency division output.

The frequency division signals for VCO counter and reference frequency counter can be switched

depending on FC status. (See Table 1)

fr > fm

fr = fm

fr < fm

FC to VCC

CPOUT TESTOUT

L

fr

Z

fr

H

fr

FC to GND

CPOUT TESTOUT

H

fm

Z

fm

L

fm

Table 1

Z: High-impedance

H: High

L: Low

fr: Reference frequency counter output frequency

fm: VCO counter output frequency

8. LOCK DET (Pin 39)

This pin detects PLL lock status. When PLL is not locked, the pin voltage is not set; when locked, it is 2V DC.

Note) • The voltages mentioned are for supply voltage of 3 V, load current of 100 µA.

• A thin pulse will be observed on monitoring this pin with an oscilloscope, but this is normal.

—13—

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