PHD101NQ03LT Просмотр технического описания (PDF) - NXP Semiconductors.
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PHD101NQ03LT Datasheet PDF : 13 Pages
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NXP Semiconductors
PHD101NQ03LT
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped)
SOT428
E
A
b2
y
A
A1
D1
HD
mounting
base
L2
b1
2
1
L
3
b
e
e1
wM A
L1
c
E1
D2
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A
A1
b
b1
b2
c
D1
D2
min
E
E1
min
e
e1
HD
L
L1
min
L2
w
y
max
mm
2.38
2.22
0.93
0.46
0.89
0.71
1.1
0.9
5.46 0.56 6.22
5.00 0.20 5.98
4.0
6.73
6.47
4.45 2.285 4.57
10.4
9.6
2.95
2.55
0.5
0.9
0.5
0.2
0.2
OUTLINE
VERSION
IEC
SOT428
REFERENCES
JEDEC
JEITA
TO-252
SC-63
Fig 14. Package outline SOT428 (DPAK)
EUROPEAN
PROJECTION
ISSUE DATE
06-02-14
06-03-16
PHD101NQ03LT_4
Product data sheet
Rev. 04 — 9 June 2009
© NXP B.V. 2009. All rights reserved.
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