MT90224AG2 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT90224AG2

T1/E1/J1 Single Chip Transceiver

Zarlink Semiconductor Inc 

MT90222/3/4

Data Sheet

MT90222 Pin Description (continued)

Pin #

Name I/O

Description

B7,A7,D8,C8,

B8,D9,C9,B9

sr_d

I/O Static Memory Data Bus. Data Bus to exchange data between the MT90222 and the

[7:0]

external static memory. sr_d[7:0] has internal weak pull-downs.

A9,C10,B10,

A10,C11,D11,B

11,A11,C12,D1

2,B12,A12,C13,

B13,A14,B14,C

14,A15,B15

D15

sr_a

[18:0]

sr_we

A16,B16

sr_cs_1, 0

O Static Memory Address Bus. Address bus on the external static memory.

O Static Memory Read/Not Write. If low, data is written from the MT90222 to the

memory. If high, data is read from the memory to the MT90222.

O Static Memory Chip Select Signal. Active low.

Processor Interface Signals

AE8,AD8,AF7,

AE7,AD7,AC7,

AF6,AD6,AF5,A

E5,AD5,AE4,A

F3,AD4,AE3,AF

2

AE12,AC12,

AF11,AE11,

AC11,AD11,

AF10,AE10,

AD10,AF9,

AE9,AD9

AF12

AD13

AE13

AC9

U25,

Y23,

AE21,

AD17

L24,

G25,

A25,

B20

up_d

[15:0]

up_a

[11:0]

up_r/w

or

up_wr

up_oe

or

up_rd

up_cs

up_irq

DSTo

[12]

[8]

[4]

[0]

DSTi

[12]

[8]

[4]

[0]

I/O Processor Data Bus. Data Bus to exchange data between the MT90222 and a local

processor.

I Processor Address Bus. Used to select the internal registers and memory locations

of the MT90222.

I Processor Read/Not Write (Motorola Mode). This is an input signal. If low, data is

written from the processor to the MT90222. If high, data is read from the MT90222 to

the processor.

Processor Not Write (Intel Mode). This is an input signal, active low. If low, data is

written from the processor to the MT90222.

I Output enable (Motorola Mode). This is an input signal. This signal should be tied to

GND for Motorola timing mode.

Processor Read (Intel Mode). This is an input signal, active low. If low, data is read

from the MT90222.

I Chip Select. This is an active low input signal. If this signal is high, the MT90222

ignores all other signals on its processor bus. If this signal is low, the MT90222

accepts the signals on its processor bus.

O Processor Interrupt Request. Open drain signal. If this signal is low, the MT90222

signals to the processor that an interrupt condition is pending inside the MT90222.

TDM Interface Signals

O Serial TDM Data Output 12, 8, 4 and 0. Serial stream which contains transmit data.

The output is set to high impedance for unused time slots and if the link is not used. It

is aligned with TXCKio and TxSYNCio.

I Serial TDM Data Input 12, 8, 4 and 0. Serial stream which contains receive data. It is

aligned with RXCKi and RXSYNCi. These pins have internal weak pull-downs.

15

Zarlink Semiconductor Inc.

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