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M66313FP Просмотр технического описания (PDF) - Renesas Electronics

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Компоненты Описание
производитель
M66313FP Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
M66313FP
Pin Arrangement
M66313FP
Parallel data
outputs
Serial data input
GND1 1
Q1 2
Q2 3
Q3 4
Q4 5
Q5 6
Q6 7
VCC 8
A9
Output enable input OE 10
Latch enable input LE 11
Direct set input SD 12
Shift clock input CK 13
Serial data output SQ32 14
Q27 15
Q28 16
Parallel data
outputs
Q29 17
Q30 18
Q31 19
Q32 20
GND3 21
Q7
Q1
Q8
Q2
Q9
Q3 Q10
Q4 Q11
Q5 Q12
Q6 Q13
Q14
A
Q15
OE Q16
LE
SD Q17
CK Q18
SQ32 Q19
Q27 Q20
Q28 Q21
Q29 Q22
Q30 Q23
Q31 Q24
Q32 Q25
Q26
42 Q7
41 Q8
40 Q9
39 Q10
38 Q11
37 Q12
36 Q13
35 Q14
34 Q15
33 Q16
32 GND2
31 Q17
30 Q18
29 Q19
28 Q20
27 Q21
26 Q22
25 Q23
24 Q24
23 Q25
22 Q26
Parallel data
outputs
Parallel data
outputs
(Top view)
Outline: 42P2R-A
Functional Description
The employment of silicon gate CMOS process of the M66313FP guarantees low power dissipation and maintains high
noise margin as well as high output current and high speed required to drive LEDs.
Each shift register bit consists of a flip-flop for shifting and an output latch.
The shift operation takes place when the clock input CK changes from low-level to high-level.
The serial data input A corresponds to the data input of the first-stage shift register, and the shift register is shifted in
sequence when a pulse is applied to CK.
The parallel outputs Q1 to Q32 are open-drain outputs.
If the latch-enable input LE is turned high–level, the content of the shift register at that instant is latched.
To expand the number of bits, use the serial data output SQ32 which shows the output of the shift register of the 32nd bit.
If the direct set input SD is turned low-level, shift register and latches are set.
If the high-level input is applied to the output enable input OE, Q1 to Q32 are set to the high-impedance state, but SQ32 is
not set to the high-impedance state. The shift operation is not affected when OE is changed.
REJ03F0179-0201 Rev.2.01 Mar 31, 2008
Page 3 of 9

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