HYB39S64800 Просмотр технического описания (PDF) - Siemens AG

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HYB39S64800

64MBit Synchronous DRAM

Siemens AG 

HYB39S64400/800/160AT(L)

64MBit Synchronous DRAM

6.2 Write Interrupted by a Read

(Burst Length = 4, CAS latency = 2, 3

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND NOP

WRITE A

READ B

NOP

NOP

NOP

NOP

NOP

NOP

CAS latency = 2

tCK2, DQ’s

CAS latency = 3

tCK3, DQ’s

DIN A0

don’t care

DOUT B0 DOUT B1 DOUT B2 DOUT B3

DIN A0

don’t care

don’t care

DOUT B0 DOUT B1 DOUT B2 DOUT B3

Input data for the Write is ignored.

7.1 Burst Write with Auto-Precharge

Burst Length = 2, CAS latency = 2, 3)

T0

T1

T2

T3

T4

CLK

Input data must be removed from the DQ’s at least one clock

cycle before the Read data appears on the outputs to avoid

data contention.

T5

T6

T7

T8

COMMAND

BANK A

ACTIVE

NOP

DQ’s

NOP

WRITE A

Auto-Precharge

DIN A0

NOP

NOP

tWR

DIN A1

NOP

NOP

NOP

tRP

*Begin Autoprecharge

Bank can be reactivated after trp

Semiconductor Group

26

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